The maxim of the superscalar architecture isthat higher performance can be achievedbyexecuting multiple instructions simultaneously. This can be realized in hardware by using a centralized instruction window. We present the design and implementation of a centralized instruction window capable of out-of-order issue and completion of four instructions per cycle. A compact layout (6.4mm by 2.2mm) of a 32-entry instruction window resulted from a full-custom design in 1.0 m (drawn) 3-layer metal CMOS technology. The layout was veri ed by simulation and shown to operate at a clock frequency over 100 MHz.