Kestrel is a programmable linear systolic array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, and eficient communication using Systolic Shared Registers. This paper describes Kestrel’s functional units in detail, and examines each of their effects on system performance. With prototypes currently in the works, we expect to complete a full Kestrel army, with between 512 and 1024 processing elements, in 1997.
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