A major constraint in high-level synthesis (HLS) for large-scale ASIC systems is memory access patterns. Typically, most stateof-the-art HLS tools severely constrain the kinds of memory references allowed in the source, requiring them to have predictable access patterns or requiring dependencies between them to be statically determinable. This paper shows how these constraints can be eliminated. We present an analysis infrastructure that can be used within any HLS toolflow for synthesizing circuits from high-level abstractions, such as ANSI-C, where no assumptions are made about memory access latencies and where dependencies between memory references can only be disambiguated dynamically at runtime (pointer aliasing). Our solution starts with a generic framework for building a dependence-aware, fully distributed, although often conservative, memory-access network (MAN) for a given memory-dependence graph. Then, we propose a suite of optimizations to customize the MAN for the given specification. All these techniques guarantee memory coherency. Experimental results on Mediabench benchmarks, show that such an approach succeeds in maintaining high levels of parallelism, while ensuring memory coherency. The optimizations succeed in lowering the synchronization overhead by as much as 4x.
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