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diagnosing errors in sequential circuits is much more difficult than that in combinational circuits because circuit unrolling is used. For example, the bug trace for the last benchmark has 77 cycles, and it produces an unrolled circuit containing more than one million standard cells. The characteristics of the benchmarks and their results are summarized in Table I. For each benchmark, 32 traces were provided, and the goal was to repair the circuit so that it produces the correct output responses for those traces. Since our algorithm processes all the traces simultaneously, only one iteration will be required. For the computation of more representative runtimes only, we deliberately processed the traces one by one and failed all verification so that all the benchmarks underwent 32 iterations. All the bugs were injected at the Register Transfer Level (RTL), and the designs were synthesized using Cadence RTL compiler 4.10. In the table, “Err. Diag. time ” is the time spent on error diagnosis, “#Fixes ” is the number of vali

Year: 2009
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