We introduce a retargetable microcode generator for applica-tion specific digital signal processors (ASDSPs). The primary goal of our work is to quickly provide system architects with the set of tools necessary for program development (assem-blers, instruction set simulators, debuggers and compilers); in particular when the processor architecture is refined si-multaneously with the algorithm. After a modification of the architecture, only the machine description written in our lan-guage nML must be altered, the tools are then produced auto-matically. The machine description need not explicitly list every possible instruction in full length. Instead, a derivation tree is described. Through the extensive use of inheritance and sharing of properties, this description can be very compact. Based on the latter, the recognition of critical data paths and the analysis of machine inherent parallelism is solely per-formed by the tool generator.