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ESTIMATION OF FUTURE MANUFACTURING COSTS FOR NANOELECTRONICS TECHNOLOGY

By Michael D. Smith, Dr. John, P. Shewchuk, Michael D. Smith, Committee Chairman, Dr. William and G. Sullivan

Abstract

In this report, a future scenario concerning the economic direction of the computing industry has been presented. This future scenario was based on past developments within the computing industry. The continued miniaturization of semiconductor components was discussed based on observed trends for transistors. The physical limitations for transistor devices were also addressed. The use of x-ray lithography for the construction of devices on a “nano-scale ” was considered. Next, cost trends within the microelectronics industry were explored. Although the cost per transistor has been observed to decrease, total equipment costs and facilities costs were observed to rise. Trend extrapolation was next used to predict the future cost per transistor and the number of transistors per chip. By taking the product of these two predicted quantities, an equation for the future manufacturing cost per chip was determined. A parametric cost estimation model (VHSIC Model) for the prediction of avionics computer system costs was modified to reflect the future performance parameters of nanoelectronics. Using data from the x86 design of Intel ® Microprocessor Chips, undetermined parameters of the Modified VHSIC Model were calculated. Next, future performance parameters were used in the model to predict the initial selling price of future chips. The resulting predictions from this model indicated that chip prices are expected to increase while the price per electronic function will decrease. Finally, profit-time models for semiconductor chips and transistors were derived. These models were used to predict the future profit for a chip or transistor

Topics: Semiconductor economics, trend extrapolation, parametric cost
Year: 1996
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.4867
Provided by: CiteSeerX
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