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Embedding binary X-trees and pyramids in processor arrays with spanning buses

By Zicheng Guo and Rami G. Melhem

Abstract

Abstract-We stiudy the problem of network embeddings in 2-D array architectures in which each row and column of processors are intercon-nected by a bus. These architectures are especially attractive if optical buses are used that allow simultaneous access by multiple processors through either wavelength division multiplexing or message pipelining, thus overcoming the bottlenecks caused by the exclusive access of buses. In particular, we define S-trees to include both binary X-trees and pyramids, and prwent two embeddings of X-trees into 2-D processor arrays with spanning buses. The first embedding has the property that all neighboring nodes in S-trees are mapped to the same bus in the target array, thus allowing any two neighbors in the embedded A--trees to communicate with each other in one routing step. The disadvantage of this embedding is its relatively high expansion cost. In contrast, the second embedding has an expansion cost approaching unity, hut does not map all neighboring nodes in S-trees to the same bus. These embeddings allow all algorithms designed for binary trees, pyramids, as well as X-trees to be executed on the target arrays. Index Terms- Alignment cost, embedding, spanning bus, pyramid, reflection index. *\--tre

Year: 1994
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.3829
Provided by: CiteSeerX
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