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Table 1 Notations in this work

By Db Rb Cb

Abstract

2 1 1,2 logic ff hold where Dlogic is the delay of the combinational logic block; CP is the clock period time; Dff is the propagation delay through the flip-flop; Dsetup and Dhold are time for data to remain stable before and after the clock triggers respectively. Definition 1. Reliable Buffered Clock Routing Tree Problem: Given clock source s0, clock sink location S ��{s 1, s2, … , sn}, and a set of skew con-straints C = {ti − tj ∈ [−NSBij, PSBij]}, build up a clock routing tree and find a set of feasible buffer locations such that the skew between any sink pairs should satisfy skew constraints C, while the influence due to wire width variations is minimized

Year: 2009
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