Skip to main content
Article thumbnail
Location of Repository

Table 1 Notations in this work

By Db Rb Cb


2 1 1,2 logic ff hold where Dlogic is the delay of the combinational logic block; CP is the clock period time; Dff is the propagation delay through the flip-flop; Dsetup and Dhold are time for data to remain stable before and after the clock triggers respectively. Definition 1. Reliable Buffered Clock Routing Tree Problem: Given clock source s0, clock sink location S ��{s 1, s2, … , sn}, and a set of skew con-straints C = {ti − tj ∈ [−NSBij, PSBij]}, build up a clock routing tree and find a set of feasible buffer locations such that the skew between any sink pairs should satisfy skew constraints C, while the influence due to wire width variations is minimized

Year: 2009
OAI identifier: oai:CiteSeerX.psu:
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • (external link)
  • (external link)
  • Suggested articles

    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.