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High Performance Low Cost Video Analysis Core for Smart Camera Chips in Distributed Surveillance Network

By Wei-kai Chan and Shao-yi Chien


Abstract — Conventional smart camera cannot achieve realtime processing for high-performance video content analysis algorithms with only RISCs. In literatures, DSPs or coprocessors are employed to implement video content analysis functions. In this paper, a video content analysis core with specially-designed hardware accelerators is proposed to realize the content analysis functions in smart camera with low cost. The resulting smart camera in this paper can then provide high performance content analysis functions, including video segmentation, video object description, and video object tracking, for real-time surveillance applications. Moreover, design techniques such as frame-level pipelining and subword level parallelism are also applied on the design of these special hardware accelerators in order to achieve high throughput rate, high hardware utilization, and saving the bus bandwidth. When considering the total hardware cost of smart camera chip, the proposed video analysis core is very low cost and is suitable to be integrated in the next generation surveillance systems. I

Year: 2009
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