This work aims to compare several IP core processor based platforms according to the following key parameters: FPGA architecture, coprocessor and accelerator integration, RTOS and HW-SW refinement tools. These key parameters are required to select a flexible and high performance IP processor core (and the associated tools) in order to implement an efficient mono-processor PACM (Processor – Accelerator – Coprocessor – Memory) architecture model. A case study for the PACM architecture model has been targeted in order to validate our key parameters. Four IP processor cores were candidate to implement the PACM architecture model. Finally, the selected ones corresponds to the Nios soft processor core within its development kit (Quartus, SOPC Builder and STRATIX device) and a shading algorithm for 3D image treatment was implemented to prove the IP processor core platform adequacy with our PACM architecture model
To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.