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Implementation and Performance Evaluation of . . .

By Joseph Maria Arul

Abstract

This dissertation presents the implementation (simulated) and evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF) architecture. Recent focus in the field of new processor architecture is mainly on Very Long Instruction Word (VLIW) (e.g., Itanium), superscalar and superspeculative designs. This trend allows for better performance at the expense of increased hardware complexity, and possibly higher power expenditures resulting from dynamic instruction scheduling. The SDF system deviates from this trend by exploring a simpler, yet powerful execution paradigm that is based on dataflow, multithreading and decoupling of memory accesses from execution. A program is partitioned into non-blocking execution threads. In addition, all memory accesses are decoupled from the thread’s execution. Data is pre-loaded into the thread’s context (registers), and all results are post-stored after the completion of the thread’s execution. Th

Year: 2001
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.2553
Provided by: CiteSeerX
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