ABSTRACT We then propose an algorithm for logic mapping that guarantees to find Highly regular, nanodevice based architectures have been proposed to a solution if one exists. We then develop a number of heuristics that replace pure CMOS based architectures in the emerging post CMOS improve the algorithm run time. era. Since bottom-up self-assembly is used to build these architectures, regular nanowire crossbars are emerging as a promising candidate. 2. MOTIVATION While these regular structures resembleCMOS programmable logic Nanowire-based crossbar structures have been proposed due to their arrays (PLAs), PLA logic synthesis methodologies fail to solve the inherent regularity. Previous research in this area has shown that two associated problems since the length and connectivity constraints im- terminal molecular diodes can be self-assembled at the crosspoints of posed by individual nanowires in these crossbars translate into chal- such a crossbar [9, 10, 11, 12, 13], thus facilitating diode-based logic. lenges hitherto not considered. These strict topological constraints Furthermore, three-terminal FET devices have also been demonstrated should be considered while mapping Boolean functions onto nanowire in . Consequently, mapping of logic functions onto the nanoeleccrossbars during logic synthesis. We develop a mathematical model for tronic crossbars will be very similar to the CMOS PLA mapping due this problem, an algorithm to solve it and three heuristics to improve to a common underlying regular crossbar structure. Notwithstanding the algorithm runtime. this apparent similarity, a number of constraints at the nanoscale im-Categories and Subject Descriptors: B.6.0 [Logic Design] pose significant differences between the nanowire-based crossbars an
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