An accurate delay model has been developed and integrated in a delay-fault test-pattern generator. The approach is based on extensive multi-input logic gate timing characterisation and layout extraction for interconnection wiring delays. The generator is capable of detecting small delay faults in combinational as well as sequential circuits. It provides the optimal observation times for detecting specific delay faults and is not limited to primitive gates. The generator has been used to provide accurate delay-fault tests for an industrial high-speed CPLD requiring all the mentioned features
To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.