This paper addresses the design and performance analysis of partial-multiple-bus interconnection networks. One such structure, called processor-oriented partial-multiple-bus (or PPMB), is proposed. It serves as an alterna-tive to the conventional structure called memory-oriented partial-multiple-bus (or MPMB) and is aimed at higher sys-tem performance at less or equal system cost. PPMEVs struc-tural feature, which distinguishes itself from the conven-tional, is to provide every memory module with I3 paths to processors (where B is the total number of buses). This in contrast to the mere s paths provided in the conventional MPMB structure (wherz g is the number of groups), suggests a potential for higher system bandwidth. This potential is fully fulfilled by the load-balancing arbitration mechanism suggested, which in turn highlights the advantages of t,h
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