Skip to main content
Article thumbnail
Location of Repository

LOW POWER CMOS OUTPUT CELL DESIGN WITH SPIKE FILTERING FOR BASEBAND DIGITAL SIGNAL PROCESSING §

By Chua-chin Wang, Ching-li Lee and Yuan-sing Chang

Abstract

A novel power-saving and small-area digital output cell is proposed in this work. The new cell drastically reduces the output power consumption by filtering pre-defined spikes, which have been considered as one of the major power dissipation sources of the whole chip, with little sacrifice of speed or delay. The duration of the spikes to be removed can be pre-defined either dynamically by digital selection signals or permanently by fuses to be burned. The maximum operating clock is 200 MHz given a 10 pF off-chip load according to measurements on silicon. Not only the proposed design removes hostile spikes to baseband DSP modules, it also reduces unwanted power dissipation caused by the spikes

Topics: baseband DSP, spike filtering, delay cells, buffering, off-chip
Year: 2009
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.8802
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://140.117.166.1/eehome/is... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.