A novel power-saving and small-area digital output cell is proposed in this work. The new cell drastically reduces the output power consumption by filtering pre-defined spikes, which have been considered as one of the major power dissipation sources of the whole chip, with little sacrifice of speed or delay. The duration of the spikes to be removed can be pre-defined either dynamically by digital selection signals or permanently by fuses to be burned. The maximum operating clock is 200 MHz given a 10 pF off-chip load according to measurements on silicon. Not only the proposed design removes hostile spikes to baseband DSP modules, it also reduces unwanted power dissipation caused by the spikes
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