Skip to main content
Article thumbnail
Location of Repository

Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing

By 

Abstract

Abstract Out-of-order issue superscalar processors can achieve very high degrees of instruction level parallelism by using a memory dependence predictor to guide dynamic instruction scheduling. With the help of the memory dependence predictor the scheduler can speculatively issue load instructions at the earliest possible time without causing significant amounts of memory order violations. For maximum performance, the scheduler must also allow full out-of-order issuing of store instructions since any superfluous ordering of stores results in false memory dependencies which adversely affect the timely issuing of dependent loads. Unfortunately, simple techniques of detecting memory order violations do not work well when store instructions issue out-of-order since they yield many false memory order violations

Topics: Memory disambiguation, store-set, wide-issue superscalar, instruction window, speculative execution
Year: 2009
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.8653
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.cs.ucr.edu/~gupta/r... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.