Caches in Chip Multiprocessors (CMPs) are organized as private L1 caches or large shared L2 cache or both. Most of the recent researchers have focused on architectural and circuit techniques to increase performance. Variable Forwarding Cache Coherency combines the advantages of private caches and shared caches, i.e., low latency of L1 and miss rate of shared L2. This paper proposes a methodology to improve performance of the system by using variable forwarding cache coherence technique in CMPs. 1
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