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An Apparatus for PseudoDeterministic Testing

By Shridhar K. Mukund, Edward J. Mccluskey and T. R. N. Rao

Abstract

In this paper we propose a new apparatus for embedding deterministic patterns in pseudo-random sequences, with application to at-speed BIST We employ an arbitrary length Shift Register driven by a LFSR (LFSWSR) with the size of the LFSR dependant only on the number of care bits in any test vectol: We provide an efJicient method to com-pute positions of bit-patterns at arbitrarily chosen tap configurations in the LFSWSR sequence. Hence, one can make an optimal choice of test segments (seeds) while tak-ing inherent advantage of don’t care bits in test vectors, say corresponding to random pattern resistant faults. The length of the LFSWSR can be arbitrarily increased to feed several interconnected logic blocks such that all the care bits of any deterministic test vector can be predictably generated without compromising computational ej@Aency.

Year: 1995
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.7888
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