It is essential to understand the impact of packaging on chips with copper/low k structures. In this paper, multi-level, multi-scale modeling technique was used to study the die attach process. Four-level models were built to analyze the packaging impact on the wafer-level behaviors. The interface fracture mechanics-based approach was adopted to predict interface delamination. The impact of thin film residual stresses was studied at both wafer level and package level. Both Plastic Ball Grid Array (PBGA) and Ceramic Ball Grid Array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. Two solutions have been suggested to prevent catastrophic delamination in Copper low-k Flip-Chip packages
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