Functional validation is one of the major bottlenecks in processor design methodology due to combined effects of increasing complexity and decreasing time-to-market. Increasing complexity of designs leads to larger set of design errors. Shorter time-tomarket requires a faster validation scheme. Simulation using functional test vectors is the most widely used form of processor validation. While existing model checking based approaches have proposed several promising ideas for efficient test generation, many challenges remain in applying them to realistic pipelined processors. The time and resources required for test generation using existing model checking based techniques can be extremely large. This report presents an efficient test generation technique using SAT-based bounded model checking. To demonstrate the usefulness of this approach, we have applied this technique to generate test programs for validation of the VLIW MIP
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