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175 GMACS/mW charge-mode adiabatic mixed-signal array processor

By Rafal Karakiewicz and Roman Genov

Abstract

An adiabatic charge-recycling mixed-signal array with integrated resonant clock generator delivers 175 GMACS (multiply-and-accumulates per second) throughput for every mW of power, a ten-fold improvement over the dynamic power incurred when resonant line drivers are replaced with CMOS drivers. The 3-T CID/DRAM cell provides non-destructive 1b-1b multiply accumulation, and integrated quantizers yield 8-bit outputs with +/- 1 LSB worst-case mismatch. The 256 × 512 four-quadrant array is embedded in a processor for templatebased face detection

Topics: adiabatic, charge-recycling, matrix-vector multiplication, pattern recognition, mixed-signal
Year: 2006
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.3953
Provided by: CiteSeerX
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