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Performance-Power Optimization of Memory Components for Complex Embedded Systems

By Catherine H. Gebotys and Robert J. Gebotys

Abstract

Optimizing performance and power during the design of embedded systems for real-time constrained applications is an important problem. This paper presents a network flow optimization technique to analyze power and performance tradeoffs for memory component design of an embedded system. The optimal number of external and internal memory accesses, memory sizes, and the number of extra computations (or data regeneration) for a number of tasks is determined. This is unlike previous research which has only discussed adhoc suggestions for this problem. The network flow approach can be solved to a globally optimal solution in polynomial time using very fast and efficient algorithms. Results for a large complex real industrial application, audio compression, donated by Motorola, show that this network flow technique provides up to 3.11 an

Year: 1997
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.3734
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