The Near Memory Processor (NMP) is a multithreaded vector processor integrated with the memory controller. The NMP works subordinately upon requests from the main processors. The NMP is complementary to the conventional superscalar processors and it is optimized for the bandwidth bounded applications and bit manipulation workloads. A program addressable memory in the NMP, Scratchpad provides an effectively large register set to hold vectors, streams and frequently accessed values. Avoiding saving and restoring the vector registers during context switch, the scratchpad reduces the overhead of the multithreading and enables a simple NMP architectural design. We design an instruction set that includes vector, streaming and bit manipulation instructions. We present the instruction set architecture of the NMP in this report, including register sets, addressing mode and instruction formats. A brief description of the benchmarks is also included. 1 The Near-Memory Processor This doucument briefly describes the ISA of the Near-Memory Processor. Figure 1 presents the NMP in the base line environment of a shared memory multiprocessor. Each memory controller is integrated with one NMP. All address space, including the NMP storage (scratchpad) is shared and can be accessed both by the main (commodity) processors and by the NMPs. The threads that the NMPs execute are called Memory Threads (MT). An MT context includes a set of registers that are described below. Not all these registers need to be saved and restored on context switching. ∗ This work is supported by DARPA Contract NBCHC-02-0056 and NBCH30390004. 1
To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.