Skip to main content
Article thumbnail
Location of Repository

Automated Logic SER Analysis and On-Line SER reduction

By et al. Andre K. Nieuwland


This paper presents a method for automated analysis of a combinational circuit to find the most SEU sensitive path, and proposes a way to make this path more robust for SEU in a low cost way

Topics: Inputs Failure rate
Year: 2004
OAI identifier: oai:CiteSeerX.psu:
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • (external link)
  • (external link)
  • Suggested articles

    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.