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Automated Logic SER Analysis and On-Line SER reduction

By et al. Andre K. Nieuwland

Abstract

This paper presents a method for automated analysis of a combinational circuit to find the most SEU sensitive path, and proposes a way to make this path more robust for SEU in a low cost way

Topics: Inputs Failure rate
Year: 2004
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.3574
Provided by: CiteSeerX
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