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Task: Communication Driven Hardware Synthesis: A New Processor Design Methodology

By Mentors M. Kishinevsky, T. Kam and L. Lavagno

Abstract

This report provides a progress update on our microarchitectural modeling of the XScale and Strongarm processors using a process-networks model of computation within the Metropolis design framework. This work provides rapid and accurate specification of microarchitectural performance models for CPU’s. In particular, we present the two major improvements from our previous report. First, we moved to a more up to date and distributable Intel-supported toolkit for compilation and functional-simulation. Secondly, we made performance optimizations that more than tripled the models ’ simulation speed. We finish by describing our planned work in refinement-based microarchitectural design space exploration, and applying our models to system-level design within Metropolis. 1

Year: 2003
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.3445
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