Abstract — In nano-based microarchitectural design, achieving higher clock frequency is confronted with thermal restrictions especially with the presense of temperature-variant leakage power. While a module temperature depends both on power density and the thermal coupling with the neighboring blocks, thermal-aware floorplans have been introduced to reduce peak temperature. The major drawback is that the thermal behavior is input application dependent. Considering average or peak power density may lead either to underestimation of the thermal crisis or to degradation in performance. To provide more realistic temperature estimation, we propose to apply multiple power profiles during floorplanning. Using the proposed statistical methods to determine the closeness between the power profiles, we apply our clustering algorithm to identify power profiles with close thermal behavior. We then generate a set of power profiles as leader power profiles to be incorporated in a thermal-aware floorplanner. Our empirical results show that using the single leader power profile (average or peak) leads to 37 % degradation in critical wire delay and 20 % degradation in wire length, compared to using the multiple leader power profiles. Our correlation metrics coupled with the clustering algorithm gives comparable improvements in the floorplanning with improved runtime as well. I
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