The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. This paper proposes a technique to reduce the power consumption of a popular low power radix-4 pipelined FFT processor by modi&ing its operation sequence. The complex multiplier is one of the most power consuming blocks in the FFT processor. The switching activity at its fixed coeflcient input can be drastically reduced by coefficient ordering and hence its power consumption. Coefficient ordering requires a novel commutator architecture which can handle the corresponding data sequencing as per new coefficient ordering. The resulting power saving is around 23 % and 9 % for the 16-point and 64-point radix-4 pipelined FFT processor respectively. This approach is very attractive for orthogonal JFequency division multiplexing (OFDW based wireless LAN (IEEE 802.1 I) requiring short FFTs but it can also be applied to the penultimate stage of longer FFTs used in Digital audio and video broadcasting'