High-speed circuits use latch-based pipelines in some of their most delay-critical parts. For latch-based pipelines, the path delay fault coverage provided by the classical approaches is often abysmally low and none of the classical design-for-testability (DFT) approaches can be used to simplify delay testing or to improve coverage. In , we presented the first DFT approach for delay testing of such pipelines. In this paper, we have developed a new theoretical framework that provides high robust delay fault coverage at low DFT overheads. We have also developed a new test generation approach that exploits this theory and any set of available DFT configurations to provide the corresponding maximum coverage for any scenario of time borrowing – expected as well as unexpected. We demonstrate the benefits of the proposed approach via extensive experiments
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