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Bridging the gap between scheduling algorithms and scheduler implementations in time-triggered embedded systems.

By Mouaaz Nahas


The scheduling of tasks in real-time, resource-constrained embedded systems is typically performed using a simple scheduler. Scheduling algorithm is the key scheduler component which determines the way in which tasks can be executed to meet their timing constraints. To ensure precise task scheduling, the right decisions about the scheduler implementation have to be made. It has been argued that there is a wide gap between scheduling theory and its practical implementation which must be bridged to achieve a meaningful validation of embedded systems.\ud The work described in this thesis attempts to address this gap by proposing a simple (generic) technique, called the Scheduler Test Case (STC), which provides the facility to explore how a particular real-time scheduler implementation can be expected to behave under a range of both normal and abnormal operating conditions. The primary focus of this thesis is on single-processor embedded systems employing Time-Triggered Co-operative (TTC) architectures. The technique proposed is a testing method which helps facilitate an empirical “black-box” comparison between the behaviour of a set of representative implementation classes of the TTC scheduling algorithm. The key criterion against which scheduler behaviour is weighed up is the system predictability manifested by predictable task execution sequence, low timing jitter and unplanned error handling capabilities. The implementation costs (including CPU, memory and power requirements) involved in creating each scheduler are also considered for distinguishing between the different TTC implementations.\ud The STC technique is then extended to provide a practical means for assessing the behaviour of multi-processor embedded designs employing Shared-Clock (S-C) scheduling architectures and TTC algorithm on the Controller Area Network (CAN) hardware protocol. In this part of the study, the STC technique explores the impact of using particular implementations of the S-C scheduler on the overall timing behaviour of multi-processor embedded systems. In addition to jitter behaviour which is measured empirically, the STC evaluates the communication behaviour by assessing the message latencies between any two communicating nodes in the network and the time frame required by the network to detect a temporary node failure. The results are expressed using mathematical equations. Moreover, the implementation costs (including network utilisation and memory overheads) are also considered to differentiate between the compared S-C schedulers.\ud The thesis finally concludes by discussing the overall findings of this project and making some proposals for future work in the area concerned with in the project

Publisher: University of Leicester
Year: 2009
OAI identifier: oai:lra.le.ac.uk:2381/4561

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