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A real-time 2 level systolic 2 D convolution chip

By Michel FOUQUES and Roger SAMY

Abstract

This paper describes the architecture of a chip for performing the 2 D convolution.\ud The systolic architecture proposed by H . T. Kung (1] has been chosen for the array of basic cells but a second level\ud of systolic architecture has been introduced with the internai structure of a basic cell . The basic cell performs\ud multiplication/accumulation in a serial way with a systolic architecture at the bit level.Cet article présente l'architecture d'un circuit réalisant l'opération de convolution bidimensionnelle, dans le cas\ud usuel d'un masque de dimension 3 x 3 .\ud Les contraintes d'intégrabilité (sous forme d'un composant VLSI) ont amené à choisir une architecture systolique\ud à deux niveaux\ud - association systolique de cellules élémentaires de multiplication-addition de mots binaires ;\ud - association systolique de microcellules opérant sur les bits

Topics: Convolution 2D, architecture systolique, intégration VLSI, 2 D convolution, Systolic architecture, VLSI integration
Publisher: GRETSI, Saint Martin d'Hères, France
Year: 1985
OAI identifier: oai:documents.irevues.inist.fr:2042/2303
Provided by: I-Revues
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