具數位校正電路之低電壓三角積分調變器設計

Abstract

[[abstract]]The supply voltage of the integrated circuits continues descending with the progress of technology so that the operational speed and performance of the digital integrated circuits are promoted. However, since the threshold voltage is not reduced proportional to the supply voltage, it reduces the required overdrive of transistors in analog circuitries. It significantly impacts the performance of the low-voltage analog-to-digital converters (ADCs) so that a strong aspiration is inspired to improve it in the modern SoC era. Delta-sigma (ΔΣ) modulators are very suitable for the realization of high resolution and high accuracy analog-to-digital converters due to its oversampling nature. It can also be found in many wireless communication applications. In this research, a ΔΣ modulator will be combined with the proposed digital correction circuits to promote the performance of the ADC operated in the low-voltage circumstance. To accomplish this research, three processes are planned as follows: (1) In the first part, explore the effect the nonidealities of the analog devices to the ΔΣ modulators, and propose an algorithm to compensate these nonidealities on analog devices to improve the performance of whole system. Verify the feasibility of the proposed algorithm and determine the optimal results by MATLAB to achieve a high resolution of ADC. (2) In the second part, we will develop a CMOS switched-opamp (SOP) that can be operated under a supply voltage of 0.8V or smaller. Then, by combining with a new low-voltage multibit quantizer and the designed SOP a new ΔΣ modulator will be proposed for the audio application. (3) In the third part, based on the proposed algorithm the digital calibration circuit will be implemented in digital form. Then, apply the developed digital correction circuit to the low-voltage ΔΣ modulator to improve the performance of the modulator.