[[abstract]]當 CMOS 電晶體之閘極尺寸持續縮小時，它的閘極絕緣層厚度將少於 1.6 nm 。在如此薄之情形下，漏電流因穿透效應將高於 1 A/cm2 ，這時就須要高介電係數 (high-k) 材料來取代傳統SiO。 但高介電係數 (high-k) 材料必須要滿足幾項需求 : (i) 與Si之熱穩定高 (ii) 與 CMOS 之傳統製程相容 (iii) 氧之滲透力低 (iv) 恰當之能階差異度 (v) 與 Si形成良好界面，以減少 interface state 與缺陷。 總言之，就是要能與基底之 Si 達到最佳之界面品質。 但高介電係數 (high-k) 材料一般而言不較傳統 SiO2 好，主要是 carrier mobility, threshold voltage , 與 trap charge 之問題須要加強， 因此我們更要積極研究界面特性，尤其是減低trap density 與高熱穩定度。 我們的研究計畫案主要是研究trap density 與 熱穩定度之問題。兩種非常特別的程序將被我們所提出用在控制在Hf-based/Si介面之 deep trap centers本研究。主要分五個研究方向: (一) 回火 (二) 控制Hf 之濃度 (三) 掺入氮原子於HfO2 (四)電性測量-利用 C-V 與 J-V測量 deep oxide traps (五) 物理特性面: 運用transmission electron microscopy (TEM), x-ray photoemission (XPS) 與 secondary ion mass spectrometry (SIMS) 來觀察Hf-O-Si 之晶格界面特性。總而言之，本研究計畫是第一個提出這兩種非常特別的程序來控制在Hf-based/Si 閘極結構中之 deep oxide traps。 兩種程序為: (一) 回火 (二) 控制Hf 之濃度， 另外三種閘極結構將考慮於本研究中 : (i) HfO2/Bulk Si (ii) HfSiO/Bulk Si (iii) HfON/Bulk Si。一旦所有的實驗結果完成，理論之呈現皆根據實驗結果。 The continuous scaling of the dimensions of complementary metal-oxide silicon (CMOS) transistors has caused the thickness of the silicon dioxide used as the gate insulator to decrease below 1.6 nm. Below this thickness, the leakage current due to direct tunneling increases above the desired values of about 1 A/cm2. It becomes necessary to replace the SiO2 with an alternative, high dielectric constant (κ) oxide. The replacement oxides must satisfy various requirements in order to act as satisfactory gate oxides. (i) thermodynamically stable in contact with the Si channel (ii) process compatible with CMOS. (iii) Oxygen diffusion should not be so large (iv) Sufficient band offsets to act as barriers for electrons and holes. (v) form a high quality interface with Si and with few interface states or defect states within the Si band gap. In short, the performance of a field effect transistor depends fundamentally on the quality of the oxide–Si interface. However, despite the intensive work on high-κ oxides, the performance of devices with high-κ gate oxides is still rather poor compared to those with SiO2 gate oxides, in terms of their carrier mobility, gate voltage threshold and trapped charge, so that a more detailed understanding of this interface is urgently needed. Hafnium based oxide films, having potential to form a silicon oxide comparable interface with the Si substrate, however, the HfO2 have shown a high interface trap density (HfO2/Si) and the HfO2 film is thermally unstable. The nature of intrinsic defects in ionic oxides differs from those in SiO2. They are oxygen vacancies, oxygen interstitials, or oxygen deficiency defects due to possible multiple valence of the metal. So far, most defects were related to the Si dangling bond on the Si side. In this proposed work, in order to fully understand the origins of the interface trap generation and deep oxide traps in Hf-based films, we propose two unique process techniques and intend to control the deep trap centers in Hf-based/Si gate stacks. A combined approach of (i) Thermal annealing treatment and (ii) Different Hf contents in HfO2 (iii) Incorporating N atomm into HfO2 (iv) Electrical characterization – C-V and J-V measurements, to study the effect of the thermal annealing and Hf contents on the interface charge and oxide charge densities in Hf-based/Si structure. (v) Physical characterization - transmission electron microscopy (TEM), x-ray photoemission (XPS), and secondary ion mass spectrometry (SIMS). The bonding structure of HfO2/Si interface at different conditions will also be investigated using X-ray photoelectron spectroscopy (XPS) to have a better interpretation of the electrical properties of the HfO2/Si structure
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