Technology Mapping for Hot-Carrier Reliability Enhancement

Abstract

As semiconductor devices enter the deep sub-micron era, reliability has become a major issue and challenge in VLSI design. Among all the failure mechanisms, hot-carrier eect is one of those which have the most signicant impact on the long-term reliability of high-density VLSI circuits. In this paper, we address the problem of minimizing hot-carrier eect during the technology mapping stage of VLSI logic synthesis. We rst present a logic-level hot-carrier model, and then, based on this model, we propose a technology mapping algorithm for hot-carrier eect minimization. The proposed algorithm has been implemented in the framework of the Berkeley logic optimization package SIS. Our results show that an average of 29.1 % decrease in hot-carrier eect can be achieved by carefully choosing logic gates from cell libraries to implement given logic functions for a set of benchmarks. It has also been observed that the best design for hot-carrier eect minimization does not necessarily coincide with the best design for low power, which has long been considered as a rough measure for VLSI reliability