How to enhance a superscalar processor to provide hard real-time capable in-order smt

Abstract

Abstract. This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications. For superscalar in-order architectures the calculation of the Worst Case Ex-ecution Time (WCET) is much easier and tighter than for out-of-order architectures. By a careful enhancement that completely isolates the threads, this capability can be perpetuated to an in-order SMT architec-ture. Our design goal is to minimise the WCET of the highest priority thread, while releasing as many resources as possible for the execution of concurrent non critical threads. The resultant processor executes hard real-time threads at the same speed as its singlethreaded ancestor, but idle issue slots are dynamically used by non critical threads. The modifications to enable SMT include a multithreaded fetch stage, an additional real-time issue stage, a wider register set, a prioritised multithreaded memory interface, split phase loads and interruptible mi-crocodes for multi-cycle operations. The application of these enhance-ments is demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.