A Methodology for the Formal Verification of FFT Algorithms in HOL

Abstract

Abstract. This paper addresses the formal specification and verifica-tion of fast Fourier transform (FFT) algorithms at different abstraction levels based on the HOL theorem prover. We make use of existing theo-ries in HOL on real and complex numbers, IEEE standard floating-point, and fixed-point arithmetics to model the FFT algorithms. Then, we de-rive, by proving theorems in HOL, expressions for the accumulation of roundoff error in floating- and fixed-point FFT designs with respect to the corresponding ideal real and complex numbers specification. The HOL formalization and proofs are found to be in good agreement with the theoretical paper-and-pencil counterparts. Finally, we use a classical hierarchical proof approach in HOL to prove that the FFT implementa-tions at the register transfer level (RTL) implies the corresponding high level fixed-point algorithmic specification.