A reconfigurable architecture for hybrid CMOS/Nanodevice circuits

Abstract

This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid “CMOL ” circuits which combine a semiconductor-transistor (CMOS) stack and two-level nanowire crossbar with molecular-scale two-terminal nanodevices (programmable diodes) formed at each crosspoint. This cell-based architecture is based on a uniform CMOL fabric, with four-transistor CMOS cells, which may be reconfigured around defective nanodevices to provide high defect tolerance. Using semi-custom design automation tools we have evaluated CMOL performance for the Toronto 20 benchmark set, so far without optimization of several parameters including the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide an advantage of more than two orders of magnitude in the area over the traditional CMOS FPGA with the same CMOS de-sign rules, at acceptable power consumption and potentially high defect tolerance