Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.Comment: ACM/IEEE Design Automation Conference (DAC), 201

Deverbal Noun Predicates of Czech Do-Constructions in a Cross-Linguistic Perspective

18819

MAAIG: Motion Analysis And Instruction Generation

Many people engage in self-directed sports training at home but lack the real-time guidance of professional coaches, making them susceptible to injuries or the development of incorrect habits. In this paper, we propose a novel application framework called MAAIG(Motion Analysis And Instruction Generation). It can generate embedding vectors for each frame based on user-provided sports action videos. These embedding vectors are associated with the 3D skeleton of each frame and are further input into a pretrained T5 model. Ultimately, our model utilizes this information to generate specific sports instructions. It has the capability to identify potential issues and provide real-time guidance in a manner akin to professional coaches, helping users improve their sports skills and avoid injuries.Comment: Accepted to the ACM Multimedia Asia 2023 Workshop on Intelligent Sports Technologies (WIST

Dynamic Finite Element Analysis on Underlay Microstructure of Cu/low-k Wafer during Wirebonding

The aim of present research is to investigate dynamic stress analysis for microstructure of Cu/Low-K wafer subjected to wirebonding predicted by finite element software ANSYS/LS-DYNA. Two major analyses are conducted in the present research. In the first, the characteristic of heat affected zone (HAZ) and free air ball (FAB) on ultra thin Au wire have been carefully experimental measured. Secondary, the dynamic response on Al pad/beneath the pad of Cu/low-K wafer during wirebonding process has been successfully predicted by finite element analysis (FEA). Tensile mechanical properties of ultra thin wire before/after electric flame-off (EFO) process have been investigated by self-design pull test fixture. The experimental obtained hardening value has significantly influence on localize stressed area on Al pad. This would result in Al pad squeezing around the smashed FAB during impact stage and the consequent thermosonic vibration stage. Microstructure of FAB and HAZ are also carefully measured by micro/nano indentation instruments. All the measured data serves as material inputs for the FEA explicit software ANSYS/LS-DYNA. Because the crack of low-k layer and delamination of copper via are observed, dynamic transient analysis is performed to inspect the overall stress/strain distributions on the microstructure of Cu/low-k wafer. Special emphasizes are focused on the copper via layout and optimal design of Cu/low-k microstructure. It is also shown that the Al pad can be replaced by Al-Cu alloy pad or Cu pad to avoid large deformation on pad and cracking beneath the surface. A series of comprehensive experimental works and FEA predictions have been performed to increase bondability and reliability in this study

Atomic-scale Structural and Chemical Characterization of Hexagonal Boron Nitride Layers Synthesized at the Wafer-Scale with Monolayer Thickness Control

Hexagonal boron nitride (h-BN) is a promising two-dimensional insulator with a large band gap and low density of charged impurities that is isostructural and isoelectronic with graphene. Here we report the chemical and atomic-scale structure of CVD-grown wafer-scale (~25 cm2) h-BN sheets ranging in thickness from 1-20 monolayers. Atomic-scale images of h-BN on Au and graphene/Au substrates obtained by scanning tunneling microscopy (STM) reveal high h-BN crystalline quality in monolayer samples. Further characterization of 1-20 monolayer samples indicates uniform thickness for wafer-scale areas; this thickness control is a result of precise control of the precursor flow rate, deposition temperature and pressure. Raman and infrared spectroscopy indicate the presence of B-N bonds and reveal a linear dependence of thickness with growth time. X-ray photoelectron spectroscopy (XPS) shows the film stoichiometry, and the B/N atom ratio in our films is 1 + 0.6% across the range of thicknesses. Electrical current transport in metal/insulator/metal (Au/h-BN/Au) heterostructures indicates that our CVD-grown h-BN films can act as excellent tunnel barriers with a high hard-breakdown field strength. Our results suggest that large-area h-BN films are structurally, chemically and electronically uniform over the wafer scale, opening the door to pervasive application as a dielectric in layered nanoelectronic and nanophotonic heterostructures.Comment: 26 pages, 5 figure