Ergin, Oguz

Karsli, B.

Ottavi, M.

Pontarelli, S.

Reviriego, P.

Yegin, S.

Skewed caches have been proposed to reduce the miss ratio on a cache by indexing the cache lines of a two way set associative cache not with the index but with a hash function of the index and the tag. This paper proposes to use ECC codes as the hashing functions that allow also correcting the stored data. It is shown that ECC behave very well as hash functions and that ECC protection provides gains in terms of error coverage with respect to state of the art skewed cache approaches

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     Edinburgh Research Explorer                                      Improving the Reliability of Skewed Caches through ECCbased HashesCitation for published version:Yegin, S, Karsli, B, Ergin, O, Ottavi, M, Pontarelli, S & Reviriego, P 2014, Improving the Reliability ofSkewed Caches through ECCbased Hashes. in 3rd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale(MEDIAN'14). pp. 28-31.Link:Link to publication record in Edinburgh Research ExplorerDocument Version:Publisher's PDF, also known as Version of recordPublished In:3rd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'14)General rightsCopyright for the publications made accessible via the Edinburgh Research Explorer is retained by the author(s)and / or other copyright owners and it is a condition of accessing these publications that users recognise andabide by the legal requirements associated with these rights.Take down policyThe University of Edinburgh has made every reasonable effort to ensure that Edinburgh Research Explorercontent complies with UK legislation. If you believe that the public display of this file breaches copyright pleasecontact openaccess@ed.ac.uk providing details, and we will remove access to the work immediately andinvestigate your claim.Download date: 05. Apr. 2019Noname manuscript No.(will be inserted by the editor)Improving the Reliability of Skewed Caches through ECCbased HashesS. Yegin, B. Karsli, O. Ergin, M. Ottavi, S. Pontarelli, P. ReviriegoReceived: date / Accepted: dateAbstract Skewed caches have been proposed to reducethe miss ratio on a cache by indexing the cache lines ofa two way set associative cache not with the index butwith a hash function of the index and the tag. Thispaper proposes to use ECC codes as the hashing func-tions that allow also correcting the stored data. It isshown that ECC behave very well as hash functionsand that ECC protection provides gains in terms oferror coverage with respect to state of the art skewedcache approaches.Keywords Error correction codes · skewed cache1 IntroductionSoft errors have been an increasingly important designissue in contemporary microprocessors. As the technol-ogy scales, circuits become more vulnerable to soft er-rors due to smaller intermediate capacitance nodes anddenser chip layouts. On-chip caches constitute an im-portant portion of the die area and are a major compo-nent for which mitigation techniques have to be imple-This paper is part of a collaboration in the framework ofCOST ICT Action 1103 “Manufacturable and DependableMulticore Architectures at Nanoscale.”This work was partially supported by the Scientific and Tech-nological Research Council of Turkey (TUBITAK) under theresearch grant 112E004.S. Yegin B. Karsli and O. Ergin are with Depart-ment of Computer Engineering, TOBB University of Eco-nomics and Technology, Ankara, Turkey {sercan.yegin, bu-rak.ibrahim.karsli}@gmail.com, oergin@etu.edu.trM. Ottavi and S. Pontarelli are with Department of Elec-tronic Engineering, University of Rome Tor Vergata, Rome,Italy {ottavi,pontarelli}@ing.uniroma2.itP. Reviriego is with Universidad Antonio de Nebrija, CallePirineos 55, 28040 Madrid, Spain previrie@nebrija.esmented. Because of the criticality of the reliability ofdata stored inside the caches, all of the stored informa-tion is commonly protected against soft errors throughError Correcting Codes (ECC) [1]. Skewed caches areproposed as an alternative to set-associate cache designin order to improve the hit rate [2]. This is accomplishedby separating the index values of different cache waysand using different hashing functions to calculate them.A hash function is any algorithm that takes an input ofarbitrary length (called a key) and maps it to a valueof fixed length (called a hash value or hash). Althougha skewed cache structure offers better performance, itincreases the size of the cache as it mandates the use ofwider tag values and hence increases the vulnerabilityof the cache structure to soft errors. In this paper, wepropose using an ECC as a hash function in a skewedcache design in order to achieve fault tolerance usingless silicon area. We show that it is possible to have theperformance of skewed cache design by using the samebit area as a regular set-associative cache.2 Set Associative Cache versus Skewed CacheDesignRegular set associative cache design is shown in Fig. 1.The index bits are used to locate the entry where thecorresponding data may be residing and the tag valuesare compared against each other to determine if thereis a cache hit. Note that in both ways of the cache, thecorresponding address locations reside on the same lineand are indexed by the same bits inside the address.Also the tag values, as well as the data, stored in thecache ways are protected by ECC. Upon each access tothe cache ways, ECC bits are checked to determine ifthere is a soft error on the stored bits. Skewed cache28       MEDIAN 2014 March 28th, 2014  −  D esden, Germany 2 S. Yegin, B. Karsli, O. Ergin, M. Ottavi, S. Pontarelli, P. ReviriegoFig. 1 Set Associative Cache Architecturedesign is proposed as an alternative to set-associativecache (shown in Fig. 2). In the set-associative archi-tecture, a location in the main memory can only bemapped to a single line inside the cache.This may result in cache conflicts as in a 2-way ar-chitecture one location in main memory can only bemapped to two locations that reside on the same set,indexed by the same bits inside the address. In order toreduce the chances of conflicts inside the cache, cacheways are indexed separately in the skewed cache designusing different hashing functions. As the results of thetwo hashing functions are different, the same addressis mapped to two different physical entries inside eachway. Skewed cache design effectively reduces the missrate [2].Skewed cache design does not use any part of thememory address for indexing; instead it uses the out-come of the hashing functions as index values to thecache ways. Because of this lack of indexing bits insidethe memory address, the size of the stored cache tagsare larger than the tags used in set-associative caches.Also the ECC bits are still stored inside the entriesmaking it mandatory to use more bits inside each en-try, when compared to the set-associative caches.3 Proposed Scheme: Using ECC as the HashingFunctionMany different hashing functions can be used to mapaddress to different locations in the cache ways. It hasbeen previously shown that XOR mapping schemes achieveless miss rates when compared to the set-associativecache design [3]. Therefore we use this design choice asbaseline in this paper. Since the ECC information isstored with each information area stored in the cache,values are encoded before they are written inside thestorage space in order to generate the ECC bits. TheError Correcting Codes used for this purpose are them-selves hashing functions that generate a bit vector fromanother input vector. As this hashing is done for faultdetection purposes, we propose to use the ECC encod-ing circuit as the hashing function of the skewed cacheand remove the stored ECC bits from the cache struc-ture all together and use the ECC bits for indexing.This is similar to the scheme proposed to protect hashtables in [4]. Fig. 3 shows the proposed architecturewhere the computed ECC bits for the tags are no longerstored inside the cache ways but instead the ECC isused as the hashing function and the computed ECCbits are used as the indexes to the cache ways. Uponreading of the tag, the read value is checked for anypossible soft errors before the stored tag is comparedagainst the tag part of the memory address for a pos-sible cache hit outcome. This new method, reduces theeffective area of the cache and makes it less prone tosoft errors as its silicon footprint is now smaller (it isless likely that a particle strike will occur as the areais now smaller). In the baseline cache (both in set asso-ciative and skewed) ECC bits are calculated before thetag value is first inserted inside the cache structure. Inour implementation, since ECC values are not storedanymore, such a computation will not be performed.Instead the proposed architecture will both encode anddecode tag bits in each access to the cache structure.The fact that the ECC encoding is now overlapped withthe hashing stage means that the delay will be similarto the baseline skewed cache architecture. By using theproposed method we are effectively reducing the size ofthe cache to the level of a set associative cache while29      Improving the Reliability of Skewed Caches through ECC based Hashes 3Fig. 2 Skewed Cache ArchitectureFig. 3 Proposed Fault Tolerant Cache Architecturekeeping the performance benefits of the skewed cachedesign.4 Evaluation MethodologyThe proposed scheme reduces the area of the cache andtherefore its vulnerability when compared to the base-line skewed cache architecture. In order to get an ac-curate idea about the performance, BCH ECC codeshave been used as hashing functions [5] as opposed tothe regular XOR hash functions. For the evaluation,we used MSIM [6], a cycle accurate microarchitecturalsimulator. In order to see the performance impact andavoid any shadowing effects of the level 1 cache on otherlevels of the cache. We applied the proposed techniqueon a 32 KB, 2 way cache with 64 bytes of data blocksand 2 cycles hit time. Spec 2006 benchmarks were runby fast forwarding 100 million and simulating 10 millioninstructions.5 Results and DiscussionsTable 1 shows the miss rates observed in the skewedcache with XOR hashing and the proposed BCH ECChashing. Results show that with the exception of dealII,which shows poor miss rates, almost all benchmarksshow cache miss rates close to skewed cache with XORhashing, with omnetpp showing slightly better results.The savings in terms of cache area for this case studywould be 8 bits per Tag as those are the bits needed toimplement a SEC-DED code on a 58 bit block [1]. Theoverall savings will be approximately 1.4% of the cachearea.30     4 S. Yegin, B. Karsli, O. Ergin, M. Ottavi, S. Pontarelli, P. ReviriegoTable 1 L1 Cache miss rates for the baseline and the proposed schemeBenchmark Skewed Cache Skewed CacheName with XOR Hashing with ECC Hashing400.perlbench 1.36% 1.36%401.bzip2 0.08% 0.08%416.gamess 0.00% 0.00%429.mcf 0.20% 0.20%433.milc 4.35% 4.35%435.gromacs 0.07% 0.07%436.cactusADM 20.19% 20.2%444.namd 0.01% 0.01%447.dealII 2.05% 3.27%454.calculix 0.17% 0.15%458.sjeng 12.50% 12.5%462.libquantum 1.92% 1.92%464.h264ref 0.00% 0.00%470.lbm 0.00% 0.00%471.omnetpp 0.18% 0.17%473.astar 2.26% 2.26%482.sphinx3 0.04% 0.04%998.specrand 0.00% 0.00%Average 2.52% 2.59%6 Conclusions and Future WorkIn this paper, we proposed an enhancement to the hash-ing functions of the skewed caches in order to improvesoft error reliability. We show that by using the ECC asthe hash function, it is possible to remove the need tostore the ECC bits thus reducing significantly the areaof the cache. Results from the spec 2006 benchmarksshow that the proposed scheme achieves a similar per-formance to the skewed cache architecture. As futurework, we want to find out how applicable is the pro-posed technique in the presence of multiple bit upsets.Furthermore, we expect to have similar results when weapply the proposed method on the higher cache levels.References1. C. L. Chen and M. Y. Hsiao, “Error-correcting codes forsemiconductor memory applications: a state-of-the-art re-view”, IBM Journal of Research and Development, vol. 28,no. 2, pp. 124-134, 1984.2. Seznec, Andr. “A case for two-way skewed-associativecaches.” ACM SIGARCH Computer Architecture News.Vol. 21. No. 2. ACM, 1993.3. Gonzlez, Antonio, et al. “Eliminating cache conflict missesthrough XOR-based placement functions.” Proceedingsof the 11th international conference on Supercomputing.ACM, 1997.4. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, “Ef-ficient Implementation of Error Correction Codes in HashTables”, Microelectronics Reliability, 2013.5. J.P. Grossman and L. Jakab “Using the BCH constructionto generate robust linear hash functions”, IEEE Informa-tion Theory Workshop, 2004.6. Sharkey, J., “M-Sim: A Flexible, Multithreaded Architec-tural Simulation Environment”, Technical Report CS-TR-05-DP01, Dept. of CS, SUNY - Binghamton, October 2005.31     

Improving the Reliability of Skewed Caches through ECC based Hashes

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Improving the Reliability of Skewed Caches through ECC based Hashes

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