Bamford, Simeon

Murray, Alan

Willshaw, David

English

Edinburgh Research Explorer

Silicon synapses self-correct for bothmismatch and design inhomogeneitiesSimeon A. Bamford1,2, Alan F. Murray3 & David J. Willshaw41: Neuroinformatics Doctoral Training Centre, University of Edinburgh;2: Complex Systems Modelling Group, Istituto Superiore di Sanità,Rome; 3: Institute for Integrated Micro & Nano Systems, University ofEdinburgh; 4: Institute for Adaptive and Neural Computation, Universityof Edinburgh.A neuromorphic chip with an array of neurons has connections(“synapses”) which implement a biological learning mechanism knownas spike-timing-dependent plasticity (“STDP”). STDP is a homeostaticmechanism which regulates the firing rate of neurons. This mechanismis shown here to reduce variation in performance between neurons, due toboth mismatch in fabrication and inhomogeneities in the electronic design.Introduction:Neuromorphic engineers create integrated circuits whichmimic neural computation in biological nervous systems. This may haveapplications in real-time, low-power, mobile processing, particularly inneural prosthetic devices. In a typical neural chip, analogue circuitsmodel the electrical behaviour of nerve cells, with currents throughtransistors physically representing currents through nervous membranes[1]. Mismatch results in variation in the excitability of integrated neurons.Although this can be representative of the variation between biologicalneurons, it is not always desirable. One way to compensate for thisvariability is calibration through programmable neural network wiring [2].However, in the connections between biological neurons (“synapses”),there is a learning mechanism in which the relative timing of spikes(the electrical pulses with which neurons communicate) from neuronsbefore and after a synapse causes changes in synaptic strength [3]. Thisspike-timing-dependent plasticity (STDP), as it is known, has interestingcomputational properties: it can detect correlations, with inputs to a neuronwhich have more correlated activity working together to strengthen theirsynapses at the expense of others which are weakened; also, when the spikerates of inputs to a neuron are raised, the strengths of its incoming synapsestend to reduce, providing negative feedback on the increase in the rate ofspikes produced, [4]. Thus STDP is a form of homeostasis, one of manyfound in biological neural networks [5]. STDP can be used explicitly asan engineering solution to ameliorate the effects of mismatch in analoguecomputations [6]. Here STDP in its native context of a neuromorphicchip is shown to partially compensate for mismatch as well as designinhomogeneites.Methods:In this work, a chip has been designed in order to investigateissues in developmental neuroscience [7]. Its silicon synapses implementSTDP; the learning rule and the circuit used are fully described in [8].To briefly describe the system, 32 neuron circuits are integrated on eachchip, each neuron had 64 dedicated circuits for incoming synapses, and 8chips were used together to create a grid of neurons. Spikes, representedas digital pulses, are received at synapse circuits and create currents inproportion to the strength of the synapse, which is stored as a voltage acrossa capacitor. These currents indirectly charge another capacitor representingthe activation of the neuron, and the neuron may then produce digital spikesof its own. The spikes cause integration of charge on other capacitorsand this short-term memory of spike arrival times is used to change thestrengths of the synapses according to the learning mechanism.0 20 40 60020406080Spike rate (Hz)Number of neurons(a)0 0.5 10204060Strength (normalised)Number of neurons(b)Fig. 1 (a) Histogram of output spike rates for the neurons (mean rate: 44 Hz,std.dev. 3.8 Hz); (b) Histogram of mean strength of all the incoming synapsesfor each neuron (mean normalised strength: 0.48, std.dev. 0.039)At every stage there is variation in the performance of different neuron andsynapse circuits, due to mismatch in integrated transistors and capacitors.To observe the effects of mismatch on the excitability of neurons, thesynapses of each neuron were connected to the same set of inputs, andtypical input was provided. Thus in a completely homogenous systemwith no mismatch, neurons should perform identically (excepting a smallcontribution of electronic noise). The input consisted of independentpoisson spike trains (20 Hz); these were generated by a PC for asimulated set of input neurons, and randomly connected to the 64 inputsynapses of each on-chip neuron. The experiment lasted 10 s. Outputspikes were streamed back to the PC to be counted. The strengthsof synapses, represented as voltages, were sequentially sampled with acustom recording system immediately after the end of the experiment.These voltages were then converted into a normalised scale based on theirmaximum and minimum possible values. Pearson correlation coefficientswere calculated, along with related one-tailed t-tests, for various groupingsof the on-chip neurons.Results:Within each neuron, the same synapse would receive the samespike almost simultaneously, as each spike is transmitted as a timedpulse on physical wires spanning each chip and reaching each synapse.During the experiment some neurons spiked more than others (fig. 1a);fig. 2(a) shows how these spike rates were distributed around the neurons.There are some broad differences between chips (inter-die variation) andsome random variation between neurons within the same chip. Thereis also systematic variation within chips, with the right-most and left-most columns of neurons spiking less than the columns in the middle;this is the result of differences in the pulse lengths at each neuron, aspulses are broadcast laterally across the chip; this inhomogeneity couldbe engineered out with careful attention to the clock distribution network[9], at the expense of design simplicity. Also, the bottom-right neuron inevery chip has a lower spike rate because some voltages in these neuronswere buffered out for test purposes, but the buffers added capacitance tothe neurons and affected their functioning; this inhomogeneity could becompensated with a more complex design.During the experiment, the strengths of the synapses quickly reduced fromtheir initial maximum level due to STDP, some more than others (fig. 1b).Fig. 2(b) gives the distribution of these weights around the neurons. Thereis an inverse relationship between the spike rate of a neuron and the meanweight of its synapses — those neurons which spiked faster ended upwith more depressed synapses (the relationship is shown in fig. 2(c); itis significant). This is the homeostatic effect of STDP in action; weakerincoming synapses make the neuron less likely to fire, providing negativefeedback on the divergence of spike rates, so the spread is not so great asit would be if not for STDP. Interestingly, this compensation worked notELECTRONICS LETTERS Vol. 00 No. 00(a) Output spike rates by neuron (b) Mean strength of synapses by neuron35 40 45 50 550.30.350.40.450.50.55Mean strength (normalised)Spike rate (Hz)(c) Correlation of spike rates and mean strengths  NeuronsMeans by chipMeans by columnMean of bottom−right cellsFig. 2 (a) Distribution of output spike rates across chips. Each rastercell is a neuron. White gaps show the boundaries between chips. Shadinggives the output spike rate, white=fastest, black=slowest. (b) Distributionof mean strengths of synapses for neurons across chips: white=strongest,black=weakest. (c) Relationship of spike rates to mean strengths. Each datapoint represents a neuron. Pearson correlation coefficient (ρ) = -0.61 (thisis significant: p=4.8× 10−28, n=256, one-tailed t-test). The mean of thecells with extra capacitance in the corner of each chip is shown; its locationdemonstrates compensation for low spike rate. Neurons are also groupedby chip, showing compensation for inter-die variation (ρ=-0.85, p=3.8×10−3, n=8, one-tailed t-test), and by column, showing compensation for clockdistribution inhomogeneity (ρ=-0.98, p=9.7× 10−3, n= 4, one-tailed t-test).just for random variation but also for the aforementioned inhomogeneitiesin electronic design. This is shown statistically for the variation betweencolumns due to pulse lengths (fig. 2(c) caption) and graphically for thecorner cells with added capacitance.Conclusion:In a neuromorphic chip, STDP has acted to reduce variationin performance between neurons, due to both mismatch in fabricationand inhomogeneities in the electronic design. This type of learningis unsupervised and self-contained; it does not require calibration. Itmay prove fruitful for electronic engineers to investigate other neuralhomeostasis mechanisms.References1 M. Mahowald and R. Douglas, “A silicon neuron,” Nature, vol. 354,pp. 515 – 518, 1991.2 E. Neftci and G. Indiveri, “A device mismatch compensation methodfor VLSI neural networks,” in IEEE Biomedical Circuits and SystemsConference (BIOCAS), 2010.3 L. Zhang, H. Tao, C. Holt, W. Harris, and M. Poo, “A critical windowfor cooperation and competition among developing retinotectal synapses,”Nature, vol. 395, pp. 37–44, 1998.4 S. Song, K. Miller, and L. Abbott, “Competitive Hebbian learning throughspike-timing-dependent synaptic plasticity,” Nature, vol. 3, pp. 919–926,Sept 2000.5 G. Turrigiano, “Homeostatic signaling: the positive side of negativefeedback,” Current Opinion in Neurobiology, vol. 17, pp. 318–324, 2007.6 K. Cameron, V. Boonsobhak, A. Murray, and D. Renshaw, “SpikeTiming Dependent Plasticity (STDP) can ameliorate process variationsin neuromorphic VLSI,” IEEE Transactions on Neural Networks, vol. 16,pp. 1626–1637, 2005.7 S. Bamford, A. Murray, and D. Willshaw, “Large developing receptivefields using a distributed and locally reprogrammable address-eventreceiver,” Neural Networks, IEEE Transactions on, vol. 21, pp. 286–304,2010.8 S. Bamford, A. Murray, and D. Willshaw, “Spike-timing-dependent plasticity with weight dependence evoked from physicalconstraints,” IEEE Transactions on Biomedical Circuits andSystems, 2012 in press; note to reviewers: this can be seen at:http://www.sim.me.uk/neural/JournalArticles/BamfordEtAl2012TBCAS.pdf.9 G. Friedman, “Clock distribution networks in synchronous digitalintegrated circuits,” Proceedings of the IEEE, vol. 89, no. 5, pp. 665–692,2001.2

A critical window for cooperation and competition among developing retinotectal synapses,”

A device mismatch compensation method for VLSI neural networks,”

Clock distribution networks in synchronous digital integrated circuits,”

Competitive Hebbian learning through spike-timing-dependent synaptic plasticity,”

Homeostatic signaling: the positive side of negative feedback,”

Large developing receptive ﬁelds using a distributed and locally reprogrammable address-event receiver,” Neural Networks,

Spike Timing Dependent Plasticity (STDP) can ameliorate process variations in neuromorphic VLSI,”

Spike-timingdependent plasticity with weight dependence evoked from physical constraints,”

Silicon synapses self-correct for both mismatch and design inhomogeneities

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