The success of neural networks in image classification has inspired various
hardware implementations on embedded platforms such as Field Programmable Gate
Arrays, embedded processors and Graphical Processing Units. These embedded
platforms are constrained in terms of power, which is mainly consumed by the
Multiply Accumulate operations and the memory accesses for weight fetching.
Quantization and pruning have been proposed to address this issue. Though
effective, these techniques do not take into account the underlying
architecture of the embedded hardware. In this work, we propose PoET-BiN, a
Look-Up Table based power efficient implementation on resource constrained
embedded devices. A modified Decision Tree approach forms the backbone of the
proposed implementation in the binary domain. A LUT access consumes far less
power than the equivalent Multiply Accumulate operation it replaces, and the
modified Decision Tree algorithm eliminates the need for memory accesses. We
applied the PoET-BiN architecture to implement the classification layers of
networks trained on MNIST, SVHN and CIFAR-10 datasets, with near state-of-the
art results. The energy reduction for the classifier portion reaches up to six
orders of magnitude compared to a floating point implementations and up to
three orders of magnitude when compared to recent binary quantized neural
networks.Comment: Accepted in MLSys 2020 conferenc