Journal ArticleThis paper presents a new random-search based integrated inductor optimization algorithm. The algorithm provides the designer with valuable information about design tradeoffs. it is used to design an inductor to minimize power dissopation in an LC VCO. The measured results show that a 53:1 power savings can be achieved over VCOs using inductors optimized only for maximum Q. Six 433-MHz VCOs were fabricated and measured. The VCO using the optimal inductor design has a measured minimum power dissipation of 1.2 mW in a 0.5-μm three-meatal CMOS process

Harrison, Reid R.

Kier, Ryan J.

English

The University of Utah: J. Willard Marriott Digital Library

Authorized licensed use limited to: The University of Utah. Downloaded on June 30,2010 at 22:11:11 UTC from IEEE Xplore.  Restrictions apply. Power Minimization of a 433-MHz Le veo for an Implantable Neural Recording System Ryan J. Kicr and Reid R. Ha rrison Depa rtment of Electrica l and Computer Engineering University o f Utah Sa lt Lake Ci ty. USA kicr@cllg.lItah.cdu Ah.vtTflL1-This pUller presents II ncw random-search based inlegr:llctl inductor optimiztllion tllgorilhm. Thc algorithm pru\'itlcs the designer wilh ,'aluable infurm atiun about t1 csign l r1ulcoffs. II is used 10 design lin inductor 10 minimize powe r dissipation in an I.e yeo. The mcasure tl results show Ihal II 53: 1 power slI\'ings clin be lIchic\'ctl o\'e r veos using ind uctors uplimi'lc tl unly for max imum Q. Six 433-MJiz veos we re fabri catctl lind measu red. Thc veo using the opl imlll inductor design has II measured minimum power dissipation of 1. 2 mW in II O. 5-I-' m three-melal CMOS Ilroccss. I. INTRODUCTION Power consumption is a troublesome issue in all wireless systems. Ln Illost cases, designers strive to reduce power consumption in order to maximize ballcry lifc and to minimizc heat gcneration. In a fully.implantable wireless system satisfaction of these two eonccms places extremely cha llenging constraints on wireless system design. All powcr tha t is gencrated by a n implanted device must be dissipated into the surrounding tissues. It has been demonstrated that power levels on the order of 10 m W are sufficient to cause significa nt temperature increases in body tissues rll. Prolonged tempemlllre increases of 5°e can lead 10 cell deml\. This presents a major problem for forthcoming flJll y· implantable wireless neural recording systems L2J. Such systems consist of approximately 100 amplifiers. signa l processing circuitry, power rectification circuitf)'. allalog· to· digital cOllverters. and a wirelcss transmiUer. a ll of which must be opemtcd on a - I O· m W power budgct and be integmted Ollto a sillgle die. This results in an undersized wireless tmnsmiller power budget (- 5 mW), within which evcn ' ultmlow powcr' systcms ca nnot operate (e.g., [3D. Therefo re wc must strivc to minimizc thc powcr dissipmion for every component of the wireless system. In thc scctions that follow, we describe the dcsign of a low-power full y-integmted LC veo. In Section II we review the methods of minimizing powcr ill LC yeO~ cmphasizing the importance of l11<lxi mizing the cquivalent parallel resisulIlce of the inductor. Ncxt. in Scction In ,,-c describe thc algori thm used to design an optima l inductor "I11is work was supported by NSF CAREER award ECS-0 134JJ6 and NlHlNtNDS contract HHSN-26520042J621C. Fabrication was provid~-d by thc MOSIS rcscaITh program. with ma:d mum parallel resistance. In Section IV we discuss the result s of the optimiza tion algorillnn. We provide measured results of a fabricatcd y e O that uses thc optimum inductor in Section V. Finally, in Section VI " 'c offer some concl usions. fl. POWER M INI/dIZATION M ETHODS IN LC YCOs Figure I shows the standa rd LC yeO topology we ha ve choscn. TIle dominant loss mechanism in the circuit is the scrics resistancc of the spiral inductor. It has becn demonstratcd that losses in thc MOS varactors lire ncgligible due to their high qua lity factors 13, 4J. A. Maxilllizarion ofRp TIle LC yeO in Fig. la ca n be modeled as a simple parallel RLC circuil. as illustrated in Fig. lb. We lump all parasiLic capacitances (Lc., Cp and C of thc inductor and Cg .... p, CgJp, and Cd"",p fo r the tmnsistors) and load capacitances into C TIle equivalence of the series and parallel RL models for the inductor is valid only ncar the resonant frequenc)' w. and it can be shown tiull the .----1 L, R m (a) L .. R , .. R~q Req = R" II-rin (b) Figur~ 1. (a) I.e VCO circuit. (b) Equil'aknt circu it. 0·7803·9390·2/06/$20.00 ©2006 IEEE 3225 IseAS 2006 Authorized licensed use limited to: The University of Utah. Downloaded on June 30,2010 at 22:11:11 UTC from IEEE Xplore.  Restrictions apply. components are related by Rp=Rs(Q2+l) Lp=Ls(Q2+l)IQ2 (1) where Q is the quality factor of the inductor given by Q = aLs IRs' (2) We do not use the definition of Q given in [5] because we employ a patterned ground shield (this has been shown to effectively eliminate the substrate loss factor), and the self-resonance factor is irrelevant when the inductor is placed in a tank circuit [5]. It can be shown that the input impedance of the cross-coupled devices is given by -rin = 11 gm = 11 JIbiasflnCoxW I L (3) where gm is the strong-inversion transconductance of the devices. If the devices are operated in moderate or weak inversion, gm becomes linearly dependent on hias. We can see from Fig. Ib sustained oscillation is achieved when Req - 0< i.e., rin=Rp. (4) The VCO power is proportional to hias and hence lIR/ assuming strong-inversion operation, as can be seen from (3) and (4). Therefore, to minimize power we must maximize Rp. B. Transistor Sizing In addition to the dependence on hias, the incremental resistance of the cross-coupled transistors is also determined by the transistor aspect ratio WIL. Therefore, we can also reduce power consumption by increasing WIL. Also, we can omit a CMFB circuit and employ cross-coupled pMOS devices. However, these approaches have limitations: the transistor Cgs is directly proportional to WIL while rin is inversely proportional to .Jw / L. As a result, the inductor self-resonant frequency (SRF) inductor and the VCO tuning range are reduced by choosing an excessively large WI L. C. Supply Voltage Scaling Perhaps the most popular method of reducing the power dissipation of any circuit is through supply voltage reduction. Indeed, VCO designs operating off of a I-V supply have been reported (e.g., [3]). Unfortunately, the supply voltage in our application (an implantable neural recording system) is fixed at 3.3 V. III. INDUCTOR OPTIMIZATION Over the years several techniques have been proposed for optimizing the design of integrated inductors e.g., [6, 7]. While these methods produce well-optimized inductors, they do not necessarily provide the designer with information about design tradeoffs. In contrast, the algorithm described below allows the designer to investigate such tradeoffs easily. A. Modeling Assumptions We employ the lumped, symmetric inductor model given in [5]. Inductances are computed using the expressions given in [8]. Substrate losses are assumed to be negligible because patterned ground shields are used. However, we do account for eddy current resistance due to the conductive substrate with the approximation offered in [9]. The inter-turn spacing s for all inductors is fixed at 2.4 !lm to satisfy design rules. We assume that the main part of the spiral is constructed by strapping together the top two layers of a three-metal process, the center tap is on the bottom metal layer, and the patterned ground shield is implemented in poly. Layer capacitance and resistivity information is taken from the MOSIS parametric data, averaged over several recent runs, for the AMI 0.5-!lm CMOS process. B. Algorithm Overview In this work, we employ an empirical, brute force approach: a guided random search. Specifically, we generate a large number of inductors that cover the inductor design space, compute their lumped-model circuit parameters, and rank them according to some performance metric. The algorithm proceeds similarly to a genetic search, however ranking is done only on a per generation basis (i.e., ranking does not consider inductors from previous generations). As a result, the algorithm does not converge on a particular solution. Instead, it traverses the design space, keeping track of the best candidates from each region. After, the algorithm has been run for many generations, we apply the ranking to the top inductors from each generation to choose the optimum solution. Clearly this technique is less computationally efficient than other methods, but with today's high speed computers computational efficiency is less important as in the past. Furthermore, since we have a list of 'good' inductors from different areas in the design space, we can easily investigate tradeoffs. C. Implementation Details Each generation starts with the top 10 inductors from the previous generation. In the first generation, these 10 inductors are chosen randomly from the entire design space. For each of these 10 inductors, 180 new inductors are generated by randomly perturbing the design parameters (diameter d, turn width w, and number of turns n) by a small amount, excluding inductor geometries that are not physically realizable. Next, model parameters such as equivalent tank resistance Rp, quality factor Q, and self-resonance frequency SRF are computed for each inductor, and the maximum quantities for each generation are used compute normalized parameters. We then score the each inductor using a weighted average of their normalized parameters, pass the top 10 to the next generation, and place the top inductor into a 'best inductor' list. After the desired number of generations, we then apply the scoring/ranking to the inductors in the 'best inductor' list to determine the optimal inductor. 3226 Authorized licensed use limited to: The University of Utah. Downloaded on June 30,2010 at 22:11:11 UTC from IEEE Xplore.  Restrictions apply. • .-i • I l l oo,f> Figure 2. Tank rcsislanc~ VCTSUS inductor selt:r~sorl<lnt frc(lucncy. '" '00 '~~-c.~, --c.,,--c.t---.t---=.c--=.---=.c--=.c--=.c-~. _'lnHl Figure 4. Tank rcsi slanc~ wn,lL$ induclan.::c. In this work we considered square and ci rcular geometries. The a lgorithm was run for 100,000 generations fo r bOIJ] geometries. We based our score on Rp- Q, SRF .. and inductor diameter with equal weighting for each parameter (the weighting for the diameter was negative to favor smaller inductors). Finally. we restricted the minimum allowable SRF 10 be twice the desired veo [requency (433 MHz) to allow for an adcqu.:1lC luning mnge and to limit frequency sensitivity due to poorly-colltrollcd pamsitic capacitances. IV OIYrlhllZATlQN RES ULTS The results of our optimization procedure aTC shown in Figs 2-5. In all of the fi gures we have highlighted sLx inductors corresponding to three interesting optimization goals: J. ) maximize Rp and minimize diameter, d. 2.) maximize Q and minimize d .. and 3.) maximize Q and minimize d for d < diameter of best inductor from goal ( 1). Square and circular geometries are considered sepanllcly. TIle parameters for these inductors are presented in Table I. The simulated yeO power corresponds to the lOO-m Ypp yeO output lcvel. ! , • o I j Figure 3. Tank resistance wrsus inductor diameter. o Figure 3. Quality lactor V~'TSuS indu~1or diameter. We can obscrve from Figs 2-5 tha t the common wisdom promoting maximizing inductor Q does not necessarily lead to beller inductors for low-power Yeos. Indeed. tile best circular inductor has an Rp , 'aille 3.2 limes larger (resulting in a yeO power di ssip<l tion 5 limes lower) than the circular inductor with lIulximulIl Q and tllC sa me outside diameter. How can this observation be reconciled with (I) where it is clear tlmt Rp is proportional to the square of Q? First, we note that the I:1miliar goal of maximizing inductor Q relics on two premises: I.) the inductance remains fi xed. and 2.) Q varies widely. However, if we allow the inductance value to vary and we recognize tha t tile range of Q factors available in integrated inductors is small (sec Fig. 5). then our observation begins to ma ke sensc. To illustrate this point further, we can rewrite the expression for Rp in ( I) as (5) which clearly illustrates tlmt, for a fixed frequency w. Rp is equally dependent on Q and L. FUrlhennorc, we clln see from Fig. 5 that the achievable range of Q is only one octave while Fig. 4 shows that L can vary over an entire decade. 3227 Authorized licensed use limited to: The University of Utah. Downloaded on June 30,2010 at 22:11:11 UTC from IEEE Xplore.  Restrictions apply. TABLE L INDUCTOR PARA)"wrnRS IndudO!· Iksigll P"nllll("IN-';; Sh"p" Opfimhtlfioll (i""ls , w • "' tJmd IUIII) (UIII) Cireular ma.~ Rp- min d 12.9 471.9 9.' 2.4 Circular max Q. mill d 8 652.8 29.7 2.4 Circular ma.x Q, mill d for d ::;: 477 8 472.2 20.1 2.4 Square ma.x Rp. min d 10.9 435.3 9.9 2.4 Square ma.~Q, mill d ,., 646.2 42.6 2.4 Squarc max Q. min d for d ::;: 477 6 472.2 30.3 2.4 Finally. we note tlllIt circular geometry o[fers lower power operation than square, though tile circular inductors must be sli ghtly larger (sec Fig. 3). Furthennore since square windings occupy more area thun circular windings with tile sa me outside diameter. tile square inductors have larger parasiLic c'lp<Jcitances and hence lower SRFs. y. MEASURED R ESULTS We have rabricated yeOs using all six inductors in Table I (see Fi g. 6). TIle power measurements ror all yeOs are listed in Table I. The minimum power dissipation was measured to be 1.2 mW, in close agreement with the simulated value. TItis veo Illis a 19% tuning mnge and phase noise or -100 dBclHz at a 600 kHz olTset. TIle tuning range and phase noise measurement s ror Ihe olher yeOs lire not yet avai lable. Further measurements arc a lso required to explain tile discrepancy between tile simulated and measured power dissipation. We believe that tlli s discrepancy is due to optimistic predict ions or R", but s-parameter measurements arc required to conlinn this suspicion. Y l. CONCLUSIONS We have presented a new inductor optimin llion algorit11m thm provides the designer with , 'aluable tradeofT MOO r ll'"r","("I(-"'; " CO Pow("r(mW>' P (fi ll I. (1111) R, (!J) Q SRF(MII;J Simultlud .11""$11",,1 r alio) 0.54 50.5 4>0 2.' 867 0.' 1.2 0.74 19.6 244 4.3 874 1.9 " 0.70 15.1 141 3.1 1409 4' 10.4 0.44 48.0 396 2.7 870 1.0 U 0.67 13.6 180 4.6 886 3.0 19.4 0.70 10.2 102 3.3 1363 8.4 63.8 inronnation. We used this algorithm 10 design an optimized inductor ror low-power yeO operation . Our results indicate that the convenLional inductor opLimization goal or simply maximizing Q docs 110t necessarily lead to maximum tank resistancc and hence minimum power dissipa tion ror rully-integmted LC yeo s. Indecd, we have shown that maximizing Rp results in lower Q inductors. LnteresLingly. these inductors 11<I VC as much as 53 times lower power dissipation tha l1 inductors optimized ror maximum Q with the same out side diameter. Finally. we observed liull circularly·shaped inductors can olTer lower power dissipation than square-shaped inductors at the cost or a modest increase in diameter. R EFERENCES PI K. Gos.~lia. 1. W~iland, 1\1. Huma~',u, aud G. l...azzi. ·'Thcrmal ele,·mion in the human evl! and head due to the operation of a rctinal prosthesis." IEEE Tran!. Biomedical Engineering. 51:1469·1477. Aug. 2004. 121 R. R. Hamson. P. T. Watkins. R. J. Kicr. R. O. LoVejoy. D. J. Black. R. A. Normann. and F. Sol:.:bach~.,. . .. 1\ low-pow • .,. intcgral~d circuil for a wireless 100·electrode neural recording system:' in Dig. Tech. Paper! 2006ISSCC pp 554·555. Feb. 2006. 131 T. Melley, A. POlTe!, C. C. Enz. and E. A. Viuoz. ··An ultralow.powcr UHF Irdnscein.,. integratL-d in a standard digital Cll"lOS process: Tral1$millcr:' IEEE J. Solid·Stale Ci~cr"t$. 36:467472, l\ lar. 200\. 141 T. Soorapanlh. C. P. Yuc. D. K. Sh.~~ffcr. T. H. I..cc, and S. S. Wong. "Analysis and opti111i7~1!ion of aecumulation·mode MOS varactor for RF ICs." In Symp. VLSI Ci~Cllil5 Dig .. pp 32·33. Jun. 1998. 151 c. P. Yue and S. S. Wong. ··Ou·chip spiral inductors with patterned ground shields for Si -bas~d RF ICs;· IEEE J. Solid·Slate Ci~cr"r$. 33:743·752, l\ lay 1998. [61 M. dd ,\ Iar 11enhcrH;()n. S. S. ,\ Iohan, S. P. Boyd, and T. H. I..c~, ··Op!imizalion of inductor circuits I' ia grometric programming,·· In. P~oc. DAC, pp 994·998, Junc 19<)<). 171 N. A Talwalkar. C. P. Yuc. and S. S. Wong. "Analysis and S)'lrlhcsis of on_chip spiral inductors. ·' IEEE T~am·. Elecrron Device!, 52: I 76. 182. Feb. 2005. 181 S. S. Mohan. M. del 1\ lar IlcrshensolL S. P. Boyd. and T. 11. Lee. ··Simple accurate e.xpressions for planar spinll inductances:· IAll· J. Solid·SIGte Clrcllirs, 34: 14 19·1424, Oct. 1999. [9J T. H. I..ce. The Design of 010S Radu).Freqllenc), lntegrared Cirelli/s. Cambridge Unil"crsily Prcss. 2004. 3228 

Power minimization of a 433-MHz LC VCO for an implantable neural recording system

https://collections.lib.utah.edu/dl_files/4c/71/4c71918fc1d48a2819b80950a5dacb010bd2ca14.pdf

Power minimization of a 433-MHz LC VCO for an implantable neural recording system

Abstract

Similar works

Full text

Available Versions

The University of Utah: J. Willard Marriott Digital Library