'Institute of Electrical and Electronics Engineers (IEEE)'
Abstract
\u3cp\u3e
This paper presents the design and measurement of a 2 × 56 Gb/s PAM-4 dual-channel electro-absorption modulator (EAM) driver in a 0.25-μm SiGe:C BiCMOS process for 3D wafer scale packaging. In this paper, a new EAM coupling method for 3D wafer scale packing is presented. The driver employs an optimized output interface with the EAM, which increases the output voltage swing by 53% while keep the same bandwidth and power consumption. The driver has 13.7 dB of gain with a 3 dB bandwidth of 31.5 GHz, which delivers 3 V
\u3csub\u3eppd\u3c/sub\u3e
at 56 Gb/s PAM-4 and consumes 364.5 mW per channel, resulting in a figure of merit of 6.5 pJ/bit.
\u3c/p\u3