Gurkaynak, F. K.

Hatirnaz, I.

Leblebici, Y.

Infoscience - École polytechnique fédérale de Lausanne

A COMPACT MODULAR ARCHITECTURE FORHIGH-SPEED BINARY SORTING. Hatrnaz, F. K. Gürkaynak, Y. LeblebiciWorcester Polytechnic InstituteDepartment of Electrical and Computer EngineeringWorcester, MA 01609-2280ABSTRACTA new algorithm and a new modular architecture arepresented for the realization of high-speed binary sort-ing engines, based on ecient rank ordering. CapacitiveThreshold Logic (CTL) gates are utilized for the im-plementation of the multi-input programmable major-ity (voting) functions required in the architecture. Theoverall complexity of the proposed bit-serial architec-ture increases linearly with the number of input vectorsto be sorted (window size = m) and with the bit-lengthof the input vectors (word size = n), and the sorter ar-chitecture can be easily expanded to accommodate largevector sets. Detailed simulations indicate that the sorterstructure can operate at sampling clock rates of up to50 MHz, where the throughput is boosted by ne-grainpipelining. It is demonstrated that the proposed sort-ing engine is capable of producing a fully sorted outputvector set in (m+n-1) clock cycles.1. INTRODUCTIONThe task of sorting an arbitrarily ordered vector set ac-cording to magnitude (either from-largest-to-smallest orfrom-smallest-to-largest) is one of the fundamental op-erations required in many digital signal processing ap-plications. It is also an expensive operation in terms ofarea-time complexity; software-based solutions requireword-level sorting and can become computationally in-tensive, while the overall complexity of hardware-basedsolutions usually increases very rapidly with the size ofthe input vector set (number of vectors) and with thebit-length of the input vectors [5], [1], [3]. The design ofecient sorting engine architectures is therefore a signif-icant challenge for overcoming the computational bot-tleneck of the binary sorting problem. A number ofrecent proposals for the realization of sorting networksrely primarily on median or rank order lters (ROF), yettheir capabilities in terms of window size and bit-lengthare typically limited due to rapidly increasing hardwarecomplexity [5], [6], [2].In this work, we present a new bit-serial sorting algo-rithm based on rank-ordering. The hardware realizationof this algorithm results in a compact and fully modularsorting engine architecture that is capable of processinga large number of input vectors in linear time (Fig. 1).The overall architecture is completely scalable to accom-modate a wide range of window sizes and bit-lengths,and the hardware complexity only grows linearly withboth of these parameters. The proposed sorter architec-ture is essentially based on a fully programmable mod-ular ROF design that was presented earlier [9]. In thefollowing, we rst present the rank ordering architecturein Section 2, followed by the proposed sorting algorithmand its hardware realization.V1V2V3V4V5V6V7V8V9rank ordering of thecurrent window elementsi-th ranked vectorin the window (Maximum filter)The largest vectorThe median vector(Median filter)The smallest vector(Minimum filter)V2V1 V7V9V3V6V8V4V5Input Vectors (words)Sliding window containing m vectors.TimeFigure 1: Illustration of the rank-ordering process.2. THE RANK ORDERINGARCHITECTUREA bit-serial algorithm rst proposed in [5] was chosen asthe basis of the programmable rank-order lter architec-ture implemented in this work. In this algorithm, theproblem of nding a rank-order-selection for n-bit longwords is reduced to nding n rank-order-selections for1-bit numbers.The algorithm starts by processing the most signif-icant bits (MSB) of the m=(2N + 1) words in the cur-rent window, through an m-input programmable major-ity gate, to yield the MSB of the desired lter output.This output is then compared with the other MSBs ofthe window elements. The vectors whose MSB is notequal to the lter output have their MSB propagateddown by one position, replacing the less signicant bitsof the corresponding words.The bit-serial operation ow of the algorithm de-scribed above suggests a simple bit-level pipelined datapath architecture, consisting of data modier-propagatorblocks to handle ne-grained data selection, and major-ity decision blocks to determine output bits.A programmable rank-order lter of any window sizeand bit-length can be realized by using the two mainblocks described above. The bit-length dictates the num-ber of the majority decision gates, whereas the windowsize determines the number of ROF-cells driving one ofthese majority gates. This regular structure results inthe ROF core array shown in Fig. 2. The programmablemajority decision gates are realized using the capaci-tive threshold logic (CTL) circuit architecture presentedearlier [4]. This allows simple implementation of pro-grammable majority gates with up to 63 parallel inputs,using a very small silicon area (625m x 130m for 63-bit majority gate).CELLROF MAJORITYDECISIONCELLROFCELLROF MAJORITYDECISIONCELLROFCELLROFCELLROF MAJORITYDECISIONCELLROFCELLROFCELLROF22 2 2pm22mm222mRank Busdata(m-1)data(m-2)data(0) coreOut(0)coreOut(m-2)coreOut(m-1)Figure 2: The ROF core as proposed in the ROF archi-tecture.The signal ow between the ROF cells and the ma-jority gates are also shown in Figure 2. The modulararchitecture consisting of only two major blocks enablesfully scalable construction of lter structures of arbi-trary size. It also forms the basis of the sorting algo-rithm described in the next section.3. THE SORTING ALGORITHMThe proposed sorting algorithm is a bit-serial algorithm,whose input is a window of m n-bit words. The out-put corresponds to a sequence of the input vectors in adesired rank order. It starts by processing the MSBs ofthe m input vectors in the current window. Each bit-plane has its own rank value which is used to calculatethe corresponding slice output.The pseudo-code of the proposed sorting algorithmis given below. The algorithm involves two loops; theouter loop initializes the rank value for the next iterationand check if the sorting operation is nished, whereasthe inner loop does the actual sorting operation by per-forming parallel instructions on n bit-planes.rankof(1):= firstDesiredRank;do{-- Rank initializationif (rankof(1) != lastDesiredRank)rankof(0):= nextDesiredRank;-- Main operation startsfor all bit-planesdo{if (all_the_bits(selectedBitplane) are in the core)then shift_rotate(selectedBitplane);elseshift(selectedBitplane);end if;selectedRank := rankof(selectedBitplane);outputWordVector(selectedRank, selectedBitplane) :=rank_order(selectedBitplane, selectedRank);rankof(selectedBitplane) :=rankof(selectedBitplane - 1);}}while (rankof(n) != lastDesiredRank)Listing of the proposed sorting algorithm.The very rst step of the algorithm is to set the rankvalue of the most-signicant bit-plane to the rst de-sired rank (rstDesiredRank), whose value depends onwhether the input vectors are to be sorted in ascend-ing or descending order. For example, if we considerthe case of sorting the input vectors in ascending or-der; at the rst iteration of the main operation loop(inner loop), the rank value corresponding to the most-signicant bit-plane (rankof(1)) has to be set to small-estRank , which results in ltering out the smallest in-put word. Also, the rank values for the next iterations(nextDesiredRank) are determined by the sorting di-rection. If sorting is in ascending order, the rankof(0)will be assigned rankof(1) + 1, until the rank valuecorresponding to the MSB-plane will be equal to theupper rank value (lastDesiredRank), which will be the largestRank . It should also be noted that the algo-rithm can be used for sorting the input vectors in anydesired order. In this case, a look-up table may be usedto provide the necessary sequence of rank values.The operations contained in the inner loop are per-formed at the same time on all bit-planes. After the mbits in each bit-plane are arranged either by shifting orby shifting&rotating, the corresponding bit-plane out-put is calculated by evaluating all of the bits in each bit-plane according to the current rank value (rank_order ).The algorithm is nished after the bit-plane correspond-ing to the least-signicant bits is processed with the lastrank value (lastDesiredRank).The operation of the proposed sorting algorithm isillustrated with an example in Fig. 3. Here, ve 4-bit vectors (A through E) are being sorted by the ROFcore. The rst rank (R1) is initialy applied to the MSBplane consisting of the bits A1 through E1. In the nextclock cycle, the same rank is used to process the lesser-signicant bit-plane (A2 through E2), while a new rank(R2) is being applied to the MSB plane. Also note thatthe staggered data bits are gradually circulated fromthe end of the chain to the front, so that each vectorin the window can be completely processed. The entireoperation requires only (m+n-1) clock cycles after allinput vectors are applied. It is important to note thatthe time-complexity of the sorting operation describedabove has a linear dependence both with respect to win-dow size (m) and with respect to bit-length (n).R2R1R2R1R3R4R2R1R3R5R2 R4R3R3 R5R4D1 C1 B1 A1A2B2C2B3 A3A4C4D3E2E3D4E4C3E1D2B4D1B1 A1 E1E2 D2 C2A2D3 C3 B3A4B4C4D4E3C1B2E4A3C1D1B1 A1 E1B2E2 D2 C2A2D3 C3 B3 A3A4B4C4D4E3E4A2B1C1B2A1E2D3C4 B4C3D2E1 D1C2B3A4A3E3E4 D4R1R4 R5R5(b)(c)(d)(a)Figure 3: Illustration of a sorting operation on ve 4-bit input vectors: (a) The staggered input vectors areshifted into the ROF core, and the rst rank (R1) isapplied to the MSB plane. (b) The MSB of the rstinput vector (A1) is rotated, R1 is applied to the nextbit-plane, and the new rank R2 is applied to the MSBplane. (c) B1 and A2 are rotated, while R1 is applied tothe lesser-signicant bit-plane. The rank R2 shifts downby one, while R3 is applied to the MSB plane. (d) Bitcirculation continues, while the ranks propagate downthe bit-planes in descending order.4. REALIZATION OF THE SORTINGENGINEThe proposed sorter architecture exploits the fact thatthe modular ROF core described in Section 2 is capableof generating one output vector per clock cycle, corre-sponding to the currently selected rank. If the rankingprocess is repeated on the same set of vectors insteadof processing a continuous stream of new vectors, themembers of the vector set can be sorted in linear timeby simply changing (increasing or decreasing) the rankin each clock cycle. The overall architecture of the sort-ing engine is shown in Fig. 4. The ow of data throughthe modular ROF core is being regulated by complemen-tary input and output shift registers, which are used tostagger the individual bit-planes of each input vectorto enable bit-level pipelined operation. The multiplexeron the input side is used for accepting the input vec-tors at the rate of one vector per clock cycle, as well asfor circulating (rotating) the data until sorting is com-pleted. The control logic is responsible for regulatingthe data circulation path, and for applying the rank se-lection signals to the individual bit-planes, in ascendingor descending order. The fact that each individual bit-plane is capable of processing a dierent rank at anygiven time signicantly increases the overall eciencyof this architecture. In a typical sorting run, the controllogic simply requests each bit-plane to process a dier-ent rank in each clock cycle, either beginning from themaximum rank and descending, or beginning from theminimum rank and ascending.ROF cells majority gatesCONTROLROFCELLROFCELLROFCELLROFCELLROFCELLROFCELLROFCELLROFCELLROFCELLINPUTSHIFTREGISTERARRAYoutputsorterdata circulation pathOUTPUTSHIFTREGISTERARRAYrank control busDATAMUXMAJORITYMAJORITYMAJORITYdata inputFigure 4: Overall architecture of the proposed sorterengine.The proposed architecture has been described withVHDL to verify its operation. Fig. 5 shows simulatedresults of two sorting operations on an arbitrarily or-dered set of eight vectors, each with a bit-length of 8bits. It can be seen that the rst output vector is gen-erated with a latency of (n-1) clock cycles, after the lastvector of the set is entered.Figure 5: Simulation results of a ranking operation onan arbitrarily ordered set of eight vectors. The inputset is being sorted in descending order from maximum(233) to minimum (11) value. The input set can also besorted in ascending order from minimum to maximumvalue, simply by changing the rank sequence applied tothe majority gates of each bit-plane.5. CONCLUSIONA modular architecture has been presented for the real-ization of high-speed binary sorting engines, based on anecient rank ordering scheme. The overall complexityof the proposed bit-serial architecture increases linearlywith the number of input vectors to be sorted and withthe bit-length of the input vectors. It was demonstratedthat the proposed sorting engine is capable of producinga fully sorted output vector set in (m+n-1) clock cycles.6. REFERENCES[1] D.S. Richards, VLSI median lters, IEEE Trans.Acoust., Speech, Signal Processing , vol. 38, pp.145-152,January, 1990.[2] W.K. Lam and C.K. Li, Binary sorter by majority gate,IEE Electronic Letters, Vol. 32, July 1996.[3] P. Wendt et al., Stack lters, IEEE Trans. Acoust.,Speech, Signal Processing , pp. 898-911, 1986.[4] Y. Leblebici, F.K. Gurkaynak, D. Mlynek, A compact31-input programmable majority gate based on capaci-tive threshold logic, in Proc. IEEE Int. ASIC Confer-ence 1998 , pp. 281-285.[5] B.K. Kar, D.K. Pradhan, A new algorithm for orderstatistic and sorting, IEEE Trans. on Signal Processing ,vol. 41, pp.2688-2694, August 1993.[6] C.C. Lin, C.J. Kuo, Fast response 2-D rank order algo-rithm by using max-min sorting network, InternationalConference on Image Processing 1996 , Vol. 1, pp. 403-406.[7] C. Chen, L. Chen, T. Chiueh, J. Hsiao, An ecientpipelined VLSI implementation of rank order lter, IS-SIPNN 1994 , Vol. 2, pp. 630-633.[8] C.L. Lee and C.W. Jen, Bit-sliced median lter designbased on majority gate, in Proc. Ins. Elec. Eng.-G, vol139, pp.63-71, 1992.[9] . Hatrnaz, F.K. Gurkaynak, Y. Leblebici, A modu-lar and scalable architecture for the realization of high-speed programmable rank-order lters, ASIC/SOC'99Proceedings, pp. 382-386, 1999.

A Compact Modular Architecture for High-Speed Binary Sorting

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