AbstractOscillograph is one of the necessary measurement instruments in modern electronic design field. A new type of Oscillograph based on FPGA is proposed and designed in this paper. It consists of oscillograph, logic analyzer and signal generator. The resolution of the oscillograph is 8 bit and the maximum value can reach 200Mbps with support of software based on windows operation system. That of the logic analyzer is 100 Msps with 16 channels. The resolution of signal generator is 140Msps with 10-bit

Haoran, Hu

Fei, Zhang

Hu Haoran

Zhang Fei

MUCC (Crossref)

Design of New Oscillograph Based on FPGA

Kröner, Fr.

Digitale Sammlungen - Goethe-Universität Frankfurt am Main

Die Kartoffel ein Weltfahrer

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Procedia Engineering

Elsevier - Publisher Connector 

Procedia Engineering 23 (2011) 60 – 64
1877-7058 © 2011 Published by Elsevier Ltd.
doi:10.1016/j.proeng.2011.11.2465
Available online at www.sciencedirect.com
Available online at www.sciencedirect.com
Procedia
Engineering
   Procedia Engineering  00 (2011) 000–000
www.elsevier.com/locate/procedia
Design of New Oscillograph based on FPGA 
Hu Haoran，ZHANG Fei 
School of Computer & Information,  Anqing Teachers College,  Anqing 246011,China 
Abstract 
Oscillograph is one of the necessary measurement instruments in modern electronic design field.A new type of 
Oscillograph based on FPGA is proposed and designed in this paper.It consists of oscillograph,logic analyzer and 
signal generator.The resolution of the oscillograph is 8 bit and the maximum value can reach 200Mbps with support 
of software based on windows operation system.That of the logic analyzer is 100 Msps with 16 channels.The 
resolution of signal generator is 140Msps with 10-bit. 
© 2011 Published by Elsevier Ltd. 
Selection and/or peer-review under responsibility of [name organizer]
Key words: FPGA; Oscillograph; DA 
Integrated oscilloscope is an integrated digital storage oscilloscopes, signal generators, logic analyzers 
a new oscilloscope. With the increasing complexity of modern electronic systems, the test parameters of 
the circuit more arduous task, in many cases, need to read, analyze multi-channel analog and digital 
signals. At this time, often need to use the oscilloscope, logic analyzer and signal generator. In analyzing 
the protocol signal, particularly in the case. In this case, the traditional analog oscilloscope has become 
increasingly inadequate, while equipped with a digital storage oscilloscope, logic analyzer, signal 
generator, not only the high cost, and the system difficult to integrate. In traditional digital storage 
oscilloscope basis, we designed and implemented a new integrated FPGA-based digital oscilloscope, well 
have to solve this problem. This paper discusses in detail the scope of which the design principles, key 
technologies and the overall solution.  
1 .   System structure
System architecture shown in Figure 1, the system uses a flexible PC - lower computer system, the 
computer is responsible for man-machine interface, process control and other tasks, microcontroller, 
FPGA is responsible for enforcement.
Open access under CC BY-NC-ND license.
Open access under CC BY-NC-ND license.
61Hu Haoran and ZHANG Fei / Procedia Engineering 23 (2011) 60 – 642 Author name / Procedia Engineering 00 (2011) 000–000 
Figure 1 System Architecture
When performing the task of digital storage oscilloscope, the first by the computer through the USB 
interface, the instrument is initialized. The FPGA based computer side of the command, perform high-
speed sampling of the relevant control. Can be 10K ~ 100Mb sampling rate (or merger of the two 
channels, so you can achieve the highest sampling rate 200Mb), high-speed acquisition of the input signal.  
Signal is first stored in the high-speed SRAM, and was only sent to the computer terminal, for storage, 
processing, analysis, display.  
When performing the task when the signal generator, first you need to set the waveform parameters, 
such as the selected waveform, frequency, amplitude, etc., detailed computer then calculates the 
parameters and the voltage value of each point. Then through the USB interface to transfer data to the 
next crew. FPGA based computer side of the command, data, control high-speed DA with a high rate 
(between the 1M ~ 140M can be adjusted) send precalculated data to complete the work described 
waveform.  
Perform the task logic analyzer is the first by the computer through the USB interface, the instrument 
is initialized. FPGA based computer side of the command, perform high-speed sampling of the relevant 
control. The sampling rate can be 200M, high-speed acquisition of the input signal. 
 2 .   Circuit Design and Implementation  
The system includes: high-speed A / D converter, high-speed D / A converter, FPGA, high-speed 
SRAM, USB communication circuits, power circuits, analog processing-related circuit, oscillation circuit. 
 The key circuit design are described below:  
Front-end circuit design: digital storage oscilloscope front-end circuit design is critical, here, we use to 
replace reed relays, self-designed front-end attenuation, amplifier, to achieve good results.  
As local circuit for the front-end: 
Figure 2 Front-end buffer stage circuit 
Computer USB Oscilloscop
High-speed AD
High-speed DA 
Logic acquisition
62  Hu Haoran and ZHANG Fei / Procedia Engineering 23 (2011) 60 – 64 A thor n me / Procedia Engineering 00 (2011) 000–000 3
The actual frequency characteristics of the corresponding simulation are as follows: 
Figure 3 Simulation of the frequency curve 
System timing control circuit design:  
Timing circuit is mainly responsible for generating system clock, and to coordinate the system part of 
the work steps. It is based on computer side of the command, resulting in different AD conversion 
sampling clock, and matching the corresponding AD converter output interface timing. Also control the 
memory read and write pulses.  
High-speed sampling, when the timing is very strict and important, so to fine-tune the timing phase, 
the amount of delay. Instrument specific workflow: receiving a command to the host computer after, AD 
conversion start doing, collecting data, and is written to memory. Timing generating circuit needs to 
provide AD chip, SRAM chip clock corresponding to the SRAM provides the address of each clock + 1. 
If not triggered, increasing memory address, when you reach the end of the memory address after the 
return address again the first side. If the trigger logic is triggered, the timing trigger generation circuit 
began to record moments of address, as well as sample length, until the user to set the record length, stop 
work and notify the computer sampling has been completed.  
When the computer receives the notification of completion of sampling, the samples began to read the 
contents of the storage area. Timing generating circuit according to the trigger time of the address records, 
as well as sample length, appropriate data can be read and stored into the computer's memory left for 
further processing, display. After the computer to inform the next crew to re-initialize, start the next 
sample. The process must be repeated continuously, a continuous waveform can be collected, processed, 
displayed! 
3.    Software Design  
Software technology is a key technology integrated oscilloscope system. We use the VB + C software 
architecture. The underlying design of the C API, complex hardware is responsible for control and 
operation to ensure that the system of real-time requirements; user interface design using VB, to speed up 
the development cycle. This combination not only simplifies the software design complexity, but also to 
ensure the performance of the system. Practice has proved that this is an effective framework, allows us in 
just six months, it developed the three components (oscilloscope, signal generator, logic analyzer) 
software system.  
The key technology is to make a smooth call VB DLL C-based design of dynamic link libraries.  
We use the following statement to achieve this functionality:  
Option Explicit  
'API declarations  
63Hu Haoran and ZHANG Fei / Procedia Engineering 23 (2011) 60 – 644 Author name / Procedia Engineering 00 (2011) 000–000 
Private Declare Function OpenDevice Lib "EZDSO.DLL" (ByVal iIndex As Long) As Long  
Private Declare Sub CH341CloseDevice Lib "EZDSO.DLL" (ByVal iIndex As Long)  
Private Declare Function EzDSOWriteData Lib "EZDSO.DLL" (ByVal iIndex As Long, oBuffer As 
Byte, ioLength As Long) As Long  
And so on.  
One EZDSO.DLL the DLL name. If a parameter in the VC and an array declared as a pointer, do not 
add ByVal, otherwise it must be coupled with ByVal. Is followed by the parameter name, type.  
4 .   Results  
Instruments of performance test results are as follows: 
Figure 4 Square-wave signal test equipment 
Sample Rate Range: 200K ~ 100M sp s. Through the merger channel, up to the 200M sp s sampling 
rate.
Sampling resolution of 8 bit. Chip memory capacity of 512 KB. 
 
Figure 5 Test to the logic signal 
Logic analyzer sampling rate 200 Msps, contains 16 channels.
64  Hu Haoran and ZHANG Fei / Procedia Engineering 23 (2011) 60 – 64 A thor n me / Procedia Engineering 00 (2011) 000–000 5
 
Figure 6 Signal generator's output signal 
Arbitrary signal generator sampling rate 140Msps, a resolution of 10bit.  
5.    Conclusions  
This paper presents the design of a new oscilloscope, the oscilloscope integrates common digital 
oscilloscope, logic analyzer and arbitrary waveform signal generator functions. Integration of virtual 
instrument technology, the use of computers as human-machine interface, have greatly improved the 
instrument's scalability.  
6.   Acknowledgment 
The work is supported by the Natural Science project of Anhui province Education Department of 
China under Grant Nos. KJ2007B155. 
References 
[1] Jiang Xue-Song, Zhang Hai-Feng. Programmable logic devices and EDA design techniques. Beijing: Mechanical 
Industry Press, 2006.5-7  
[2] Wang Cheng, Wu Ji-Hua, Fan Li-Zhen, Xue Ning, Xue Xiao-Gang. Altera FPGA/CPLD Design (Fundamentals). Beijing: 
People's Posts & Telecom Press, 2005.11-13  
[3] Wang Zhi-Peng. Programmable logic device design principles and procedures. Beijing: National Defense Industry 
Press .2007.16-18  
[4] Huang Zhi-wei. FPGA system design and practice. Beijing: Electronic Industry Press .2005.15-19  
[5] Li Hong-Wei, Yuan Si-hua. Quartus II based on the FPGA/CPLD design. Beijing: Electronic Industry Press .2006.19-20 
[6] Ravi Gupta. Linux 2.6 for Embedded Systems - Closing in on real time. RTCMagazine 2003 (10) 


Design of New Oscillograph Based on FPGA 

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Design of New Oscillograph Based on FPGA

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