Design includes multi-channel replicator which can reduce chip-writing requirement, selective annihilating switch which can effectively annihilate bubbles with minimum delay, and modified transfer switch which can be used as selective steering-type decoder

Chen, T. T.

English

NASA Technical Reports Server

October 1975	 B75-10222 
NASA TECH BRIEF 
Langley Research Center 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
A 1-1/2-Level On-Chip-Decoding Bubble Memory Chip Design 
A 1-1/2-level bubble memory on-chip decoder 
circuit has been designed which can perform the 
on-chip decoding function and may be fabricated with 
a gross alinement requirement. This design includes a 
multiple-channel replicator which can reduce the 
chip-writing power requirement, a selective annihilat-
ing switch which can effectively annihilate bubbles 
with minimum delay, and a modified transfer switch 
which can be used as a selective steering-type decoder. 
In the bubble memory organization, the on-chip 
decoding approach has the advantages of lower access 
time than serial or major/minor loop organization, a 
small number of control leads, and inherent 
redundancy capability. For device processing, the 
single-level circuit approach, with gross alined 
conductor pads, simplifies the process procedure and 
increases the yield. This design presents a 1-1/2-level 
on-chip decoding circuit which combines the advan-
tages of both approaches. 
There are two basic on-chip decoder organizations 
in the design. In both, the bubbles are separated by a 
series of generators and are replicated by a set of 
multiple replicators, so that there is one stream of 
bubbles propagating toward each storage loop. Before 
reaching the storage loop, these bubble streams pass a 
set of selective annihilating switches, which will 
annihilate every bubble stream except the selected 
one. In this manner, the information is written into 
the particular loop selected. 
To read out a particular loop, there are two 
different approaches. For one, the information in all 
storage loops is replicated simultaneously by a set of 
replicators. These bubble streams are then selectively 
annihilated by a set of switches which allows only one 
selected stream to reach the multiple-input detector. 
In the other design, the bubble streams pass a set of
steering switches which allows only a selected stream 
to reach a replicator leading to the multiple-input 
detector. The rest of the stored information will be 
steered back to the storage loop before reaching the 
replicator. 
Since the decoder circuit single-level generator, 
replicator, and multiple-input detector components 
are already established, only the multiple-channel 
replicator, the selective annihilating switch, and the 
selective steering switch will be covered here. 
a. Multiple-Channel Replicator - Entered bubbles 
are expanded by chevron elements and are propa-
gated toward several parallel channels. At the last 
column of the stretcher area, part of the chevron 
elements is connected by Permalloy lines through 
which a current pulse can be passed. This current 
pulse generates field gradients which split the 
stripe domain. Thus, a single input can be repli-
cated into several identical outputs. The replicator 
reduces the number of generators in the circuit 
and can reduce, also, the required writing power of 
the chip. 
b. Selective Annihilating Switch - The basic anni-
hilator consists of one Permalloy line across the 
chevro,n propagation element. If this line is placed 
at the first half of the chevron, a positive current 
pulse will only collapse bubbles at that portion of 
the chevron but not the bubble at the other end. 
The reverse is true if the Permalloy line is placed at 
the other half of the chevron, as then a negative 
current pulse can annihilate bubbles in that por-
tion. By placing the conductor Permalloy at differ-
ent'positions and by using a bipolar current pulse, 
a decoder line is achieved. In combining sets of 
such decoder lines, one can effectively select any 
one loop out of a number of loops. 
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration, Neither the United States 
Government nor any person acting on behalf of the United States
(continued overleaf) 
Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19750000222 2020-03-19T20:30:03+00:00Z
c. Selective Steering Switch - This switch design is 
a modification of the existing single-level transfer 
switch. The input bubble stream has two alterna-
tive paths, depending on whether the transfer 
switch is active or not. Replacing the nonfunction-
al part of the Permalloy lead with a conductor lead 
completely avoids the Permalloy crossover prob-
lem. The transfer switch can be integrated into a 
selective annihilating decoder switch. Using the 
conductor lead as an inactive element, two com-
plementary switch lines form a decoder line. 
Therefore control lines will be able to select storage 
loops.
Note: 
Requests for further information may be directed 
to:
Technology Utilization Officer 
Langley Research Center 
Mail Stop 139-A 
Hampton, Virginia 23665 
Reference: B75-10222 
Patent status: 
Title to this invention has been waived under the 
provisions of the National Aeronautics and Space Act 
[42 U.S.C. 2457(f)], to the Rockwell International 
Corporation, 3370 Miraloma Avenue, Anaheim, 
California 92803.
Source: Thomas T. Chen of

Rockwell International Corp.

(LAR-11766) 
Categories: 01 (Electronics - Components 
and Circuitry) 
B75-10222	 02 (Electronics Systems)


A 1-1/2-level on-chip-decoding bubble memory chip design

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