Decoder circuit with complementary-symmetry circuit configuration composed of MOS and n-p-n bipolar devices minimizes power consumption. Emitter-follower drive scheme results in low power dissipation and high speed operation

Katz, S.

English

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October 1970	 Brief 70-10372 
NASA TECH BRIEF H 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage commercial 
application. Tech Briefs are available on a subscription basis from the Clearinghouse for Federal Scientific and Technical 
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be directed to the Technology Utilization Division, NASA, Code UT, Washington, D.C. 20546. 
Integrated Circuit Random-Access Memory Decoder 
The problem: 
Develop a decoder, for use in a medium-speed 
random-access memory, which consumes negligible 
power and exhibits low output impedance, and to 
maintain compatibility with present integrated cir-
cuit (IC) technology.
-V	
-VS 
Schematic of Basic 32-Output BIMOS Decoder 
The solution: 
Using a complementary-symmetry circuit configura-
tion composed of MOS and n-p-n bipolar devices 
minimizes power consumption. An emitter-follower 
output stage provides low output impedance. The
M OS transistors are p-channel enhancement-mode 
devices. 
How it's done: 
The circuit shown in the figure has a five-bit binary 
input with corresponding address complements. When 
a given address signal is applied to lines A-A, B-s, 
C-C, D- and E-E, only one path, comprised of five 
p-channel transistors, conducts. Because the strobe 
signal is at ground potential during the quiescent state, 
the n-p-n bipolar devices are biased in the ON state, 
and all output devices are forced to the negative supply 
voltage, -V5
. Upon command (-Vs on strobe terminal), 
the common p-channel strobe-controlled transistor 
activates the selected address line and switches the 
output of that address line to ground. The other 31 
unselected outputs remain at the negative supply volt-
age. When the strobe signal returns to ground poten-
tial, the selected output voltage reverts to -Vs. The 
maximum width of the strobe pulse is limited by the 
time required for unselected lines to discharge to 
ground. Because of the complementary structure, 
quiescent power dissipation is negligible and circuit 
operation is essentially independent of device param-
eters. The common source-drain connections inher-
ent in MOS ICs enable the bipolar devices to function 
as output units with a minimal use of silicon areas; 
additional space is conserved by incorporating a MOS 
device, in place of a diffused resistor, to drive the base 
of the bipolar transistor. 
Notes: 
I. The decoder circuit with an emitter-follower 
drive scheme results in low power dissipation and 
high speed operation. This circuit should find wide 
use in integrated low power memory systems and in 
applications where a decoder must drive a high 
capacity line in short time periods. (continued overleaf) 
This document was prepared under the sponsorship of the National 	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States 	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States	 will be free from privately owned rights.
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2. The following documentation may be obtained 
from:
Clearinghouse for Federal Scientific 
and Technical Information 
Springfield, Virginia 22151 
Single document price $3.00 
(or microfiche $0.65) 
Reference: 
NASA-CR-86 115 (N69-14036), Research 
to Develop Data Storage
Patent status: 
Inquiries about obtaining rights for the commercial 
use of this invention may be made to NASA, Code 
GP, Washington, D.C. 20546.
Source: S. Katz of

Radio Corporation of America

under contract to

Electronics Research Center

(E RC- 1021 1)
. 
.0- 
Brief 70-10372	 Category 01


Integrated circuit random-access memory decoder

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