Encoding algorithms generate a 32 x 64-bit matrix Reed-Muller code from a 6-bit orthogonal code-word. This increases error-free reception by a high rate telemetry channel under adverse signal noise with minimal use of additional hardware

Anderson, T. O.

English

NASA Technical Reports Server

September 1970
	
Brief 70-10051 
NASA TECH BRIEF 
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be directed to the Technology Utilization Division, NASA, Code UT, Washington, D.C. 20546. 
Block Encoders for Reed-Muller Codes 
X4	 X3	 0
	
X2	 Xl	 0 
Exclusive	 I	 Exclusive	 Exclusive 
OR	 I	 OR
GatGate	 e Gate	  I	
OR 
	
Register k; I Shift	 I	 ______ 	 _______________ ______	 ____________ 	 Shift	 _____ Register 1	 T 
Block Diagram Logic Circuit 
for Reed-Muller Code Scheme. 
The problem: 
To increase error-free reception by a high-rate 
telemetry channel under extremely adverse signal-
noise with minimal use of additional hardware. The 
format of the transmitted data is a block-encoded, 
6-bit orthogonal code-word. 
The solution: 
Encoding algorithms were developed for generating 
a 32 x 64-bit matrix Reed-Muller code from the 6-bit 
orthogonal code; the larger matrix increases the proba-
bility of error-free reception. Variations of logic 
circuits were designed to implement the block encod-
ing schemes. 
How it's done: 
The Reed-Muller code is constructed, as follows: 
+1 +1	 A A	 (N-I) (N-I) 
A=	 ;B=	 ;N= 
+1	 1	 AA	 (N-1) (N-1)
An orthogonal matrix of a simple two-variable code
dictionary is formed by adding the complement of the 
code in the lower right, i. e.,
Two-variable 
From the Reed-Muller code structure it may be de-
duced that each code symbol is a mod-2 function be-
tween a certain set of the original information bits; 
the selection of these sets of the original information 
bits is a simple mapping between the original infor-
mation bits and the binary sequence. In the applica-
tion, the mod-2 function is equivalent to a parity 
function which indicates whether the number of 
"ones" in a vector (i.e., in a row or column of the 
matrix) is odd or even. 
The criteria for the design of a logic circuit which 
implements the code scheme, shown in the figure, are 
based on the mod-2 algebraic expressions: 
A
s(continued overleat) 
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X® 0 =X 
xx=0 
xxx=x 
X	 X	 X	 X = 0, etc. 
Odd number of X equals X, even number X equals 0. 
If a set of variables in the shift register is continually 
shifted around and entered through the mod-2 func-
tion between the output register and another variable 
(every other cycle), and each variable in the register 
will be mod-2 added with the entry variable and every 
other time not. A mod-2 mapping between the entry 
variables and the binary sequence is obtained by 
several modules connected together by two-term mod-
2 functions. For a' large number of variables, identical 
modules can be added as required and each new 
module is clocked once every other cycle of the pre-
ceding one.
Note: 
Requests for further information may be directed to: 
Technology Utilization Officer 
NASA Pasadena Office 
4800 Oak Grove Drive 
Pasadena, California 91103 
Reference: B70-10051 
Patent status: 
This invention is owned by NASA, and a patent ap-

plication has been filed. Royalty-free, nonexclusive

licenses for its commercial use will be granted by

NASA. Inquiries concerning license rights should be

made to NASA, Code GP, Washington, D.C. 20546.

Source: Tage 0. Anderson of

Caltech/JPL
under contract to

NASA Pasadena Office

(NPO-10629 and

NPO- 10636) 
Brief 70-10051	 Category 01


Block encoders for Reed-Muller codes

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