In this paper we present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson-Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport. As a result of these calibrated results, we have established a link between channel strain and the device performance. Additionally, we have compared the current flow in a single, double and triple vertically stacked lateral NWTs

Al-Ameri, Talib

Alexander, C.

Asenov, A.

Georgiev, V.P.

Lema, Adamu

Riddet, C.

Sadi, T.

Towie, E.

English

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     Al-Ameri, T., Georgiev, V.P., Lema, A., Sadi, T., Towie, E., Riddet, C., Alexander, C., and Asenov, A. (2016) Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study. In: 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), Toulouse, France, 9-12 Oct 2016, ISBN 9781509043521 (doi:10.1109/NMDC.2016.7777117)  This is the author’s final accepted version.  There may be differences between this version and the published version. You are advised to consult the publisher’s version if you wish to cite from it.     http://eprints.gla.ac.uk/132821/            Deposited on: 14 December 2016                      Enlighten – Research publications by members of the University of Glasgow http://eprints.gla.ac.uk    Abstract— In this paper we present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson- Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport. As a result of these calibrated results, we have established a link between channel strain and the device performance. Additionally, we have compared the current flow in a single, double and triple vertically stacked lateral NWTs. I. INTRODUCTION The electron transport properties in nanowire transistors (NWTs) could be precisely engineered by introducing strain in the channel, different channel materials and also various device cross-section geometries and gate lengths. In our recently published work [1], we established a correlation between gate length, cross-sectional geometry and electrostatic driven performance in ultra-scaled nanowires. Our results show that NWTs with elliptical cross-section have the best device performance in comparison to wires with square and circular cross-section. In this work we extend our study by presenting results based on correlation between strain in the channel and device performance. Also we establish a correlation between the drive current and vertical stack of multiple-channel NWT. In order to evaluate the device performance, we employed two methods: 2D Poisson-Schrodinger (PS) coupled with drift-diffusion (DD) simulator and 3D ensemble Monte Carlo (EMC) taking in to account accurate quantum confinement obtained from PS+DD then we calibrate DD on EMC. II. METHODOLOGY AND DEVICE DESCRIPTION For the purpose of this work, we have created Si n-channel gate all around NWTs with an elliptical cross-section of 7 nm x 5 nm. All devices have 0.4nm SiO2 interfacial and 0.8nm HfO2 (High-k) layer respectively as shown in Fig.1. The doping profile has the following details: channel - 1014/cm3, extensions - 1020/cm3, and source/drain - 4x1020/cm3. Also we have simulated devices with four different gate length of 8nm, 12nm, 16nm and 20nm. Moreover, the possibility of creating a transistor with multiple parallel nanowires channels as a single device has  Talib Al-Ameri, is with School of Engineering, University of Glasgow, Glasgow, G12 8LT, UK, and also with College of Engineering at Al-Mustansiriya University, Baghdad, Iraq (e-mail: t.ali.1@research.gla.ac.uk).  V. P. Georgiev, F. Adamu Lema, T. Sadi, A. Asenov are with School of Engineering, University of Glasgow, Glasgow, G12 8LT, UK.  E. Towie, C. Riddet, C. Alexander are with Synopsys, 11 Somerset Place, Glasgow G3 7JT, UK been reported in recent publication [2]. The simulation work is divided into two main steps. The first step is based on solving Poisson-Schrödinger (PS) equations and coupling them to the  drift-diffusion (DD) module of the GSS ‘atomistic simulator’ GARAND [3]. The quasi-Fermi level from the converged DD solution is used as a fixed reference within the Poisson-Schrödinger model to transfer the current transport behaviour between solutions. The PS solution is then iterated until convergence to obtain a quantum mechanical (QM) solution of the charge density.  Next the QM charge density from the Poisson-Schrödinger solution is used to obtain a fixed ‘quantum correction’ term. The DD loop is carried out again, using the ‘quantum correction’, until convergence is obtained. In this step we have used a valley reduction technique, eliminating the upper valleys (L- and Γ- valleys) of the silicon conduction band to speed up the solution. Additionally, silicon NWTs with the simulated dimensions contain the majority of charge over the biases of interest within the first ten subbands and we therefore limit the simulated subbands to this number.  The second step start is based on 3D-EMC module of GARAND. The converged charge and potential profiles from the previous step are used as initial guess for the 3D-EMC. The QM correction is applied throughout the simulation period to maintain a self-consistent but time-varying electrostatic potential and field distributions. 3D EMC simulations provide accurate physical treatment of the non-equilibrium transport [4]in ultra-scaled channel transistors and result in accurate prediction of the ON-state transistor performance. The obtained results were used as a reference point to calibrate our DD simulator. In such a way we can used DD simulation for fast evaluation of the device properties taking into account the required physical constrains in such ultra-scaled devices. Moreover, during these calculations we have applied various channel strain values.   Fig. 1 3D schematic view a Si nanowire transistor (NTW) and material information for the two channel Si NWT. III. RESULTS AND DISCUSSIONS The upper part of Fig. 2 shows the ID-VG characteristics for NWTs with four different gate lengths of 8nm, 12 nm, 16 Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study Talib Al-Ameri, V. P.  Georgiev, F. Adamu Lema, T. Sadi, E. Towie, C. Riddet, C. Alexander. A. Asenov   nm and 20nm. All devices are single NWTs without strain in the channel. Those single NWTs were simulated by two methods: DD+PS and EMC methods. In all figures, the solid lines correspond to low drain bias (VD=0.05V) and the dashed lines are related to the high drain bias (VD=0.7V). The black solid and black dashed lines in Fig. 2 correspond to a DD solution with defaults values for the mobility parameters. From the results in Fig. 2 is clear that considering such default values for the DD simulation leads to a poor estimation of the ION current for low and high drain. The recommended option is to calibrate the parameters in DD to correctly reproduce the EMC solution which captures accurately the physics in the devices. Indeed, such calibration is achieved and it is presented with blue triangles on Fig. 2 for all gate length and drain biases. Fig. 2 (down) shows ID-VG characteristics for all gate lengths at four different applied strain levels. The applied strain can improve drive currents by 20%-45%. Top part of Fig 3 compares the ID-VG curves for NWT with a single, double, and triple channel. As it is expected the tri-channel device has higher ION current in comparison to one and two channels transistors. However, it needs to be pointed out that the current is not 3 times higher for the tri-cannels device in comparison to the one channel device.   Fig 2 (top) ID-VG characteristics for NW with gate lengths 8nm, 12nm, 16nm, and, 20nm. (down) ID-VG characteristics for NW with LG 12nm at applied uniaxial strain 0.5GPa, 1GPa, 1.5GPa and 2GPa based on EMC. Dashed lines are at VD=0.7V and solid lines are at VD=0.05V. The reason for this is clearly visible on the bottom part of Fig. 3. The bottom part of Fig 3 shows the 3D view of the current density for NWTs with single, double, and triple channels devices. The transistor with two channels has almost identical current density in both channel. However, the device with tri-channels show significant difference of the current density between the top nanowire and the bottom one. The main reason for this is that the contacts are on the top of the source and drain region which makes it easier for the current to flow through the closest nanowire channel.    Fig 3 (top) ID-VG curves of single, double, triple NW. (bottom) 3D view of the current density for NWTs wit single, duple, and triple channels with LG=12nm. Dashed lines are at VD=0.7V and solid lines VD=0.05V. IV. CONCLUSION In summary, we have simulated ultras-called NWTs with two methods: DD+PS and EMC. Based on those methods we have established a link between channels strain and the device performance. Flowed by implementation of calibration procedure of DD module using PS and EMC simulations over nanowire transistors for feature calculations of various sources of statistical variability and statistical oxide reliability in nanowire. Also we have compared the current flow in single, double and triple vertically stacked horizontal NWTs.  REFERENCES [1] Y. Wang, T. Al-Ameri, X. Wang, V. P. Georgiev, E. Towie, S. M. Amoroso, A. R. Brown, B. Cheng, D. Reid, C. Riddet, L. Shifren, S. Sinha, G. Yeric, R. Aitken, X. Liu, J. Kang, and A. Asenov, “Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3229–3236, Oct. 2015. [2] K. W. H. Mertens, R. Ritzenthaler, A. Hikavyy, M. S. Kim, Z. Tao, H. D. S. A. Chew, A. De Keersgieter, G. Mannaert, E. Rosseel, T. Schram, N. Horiguchi, A. V.‐Y. Thean, “Gate‐All‐Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates,” 2016. [3] “www.goldstandardsimulations.com.” . [4] T. Al-ameri, V. P. Georgiev, F. Lema, T. Sadi, and X. Wang, “Impact of strain on the performance of Si nanowires transistors at the scaling limit : A 3D Monte Carlo / 2D Poisson Schrodinger simulation study,” in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, pp. 213–216. 

Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study

Enlighten: Publications

Talib Al-Ameri

V. P. Georgiev

F. Adamu Lema

T. Sadi

E. Towie

C. Riddet

C. Alexander

A. Asenov

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Performance of vertically stacked horizontal Si nanowires transistors: A 3D Monte Carlo/2D Poisson Schrodinger simulation study

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Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study

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