In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13µm SiGe BiCMOS technology and a threshold tunable between ±160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a data rate of up to 80Gbps can be achieved

Bauwelinck, Johan

De Keulenaer, Timothy

Pierco, Ramses

Torfs, Guy

English

Timothy De Keulenaer

Guy Torfs

Ramses Pierco

Johan Bauwelinck

Crossref

A digitally controlled threshold adjustment circuit in a 0.13&amp;#x00B5;m SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

Ghent University Academic Bibliography

A Digitally Controlled Threshold Adjustment Circuitin a 0.13µm SiGe BiCMOS Technology forReceiving Multilevel Signals up to 80GbpsTimothy De KeulenaerGhent University,INTEC/IMECGhent, BelgiumEmail: timothy.dekeulenaer@intec.ugent.beGuy TorfsGhent University,INTEC/IMECGhent, BelgiumRamses Pierco,Johan BauwelinckGhent University,INTEC/IMECGhent, BelgiumAbstract—In this paper, a high bandwidth digitally controlledthreshold adjustment circuit is proposed which can be usedfor demodulating high-speed multi-level signals. Simulations ofthe bandwidth are presented together with measurements of thecontrol currents to indicate the threshold adjustment capability. Abandwidth above 80GHz in a 0.13µm SiGe BiCMOS technologyand a threshold tunable between ±160mV in steps of 0.6mVis achieved, allowing very precise control of the threshold level.This allows the circuit to accurately position the threshold on theeye-crossing of a high speed multi-level signals. By applying thiscircuit to demodulate a duobinary signal over a 40GHz channel,a data rate of up to 80Gbps can be achieved.I. INTRODUCTIONAdvances in the data rate of modern communication sys-tems has lead to the need for an increase in speed of inter-chip communication. Typically, a non-return-to-zero (NRZ)signal is transmitted over a PCB transmission line (microstrip,grounded coplanar waveguide), but, with rising speed, thelimited bandwidth of the channel (the transmission line) andthe maximum bandwidth that can be achieved by the chiptechnology (indicated by the maximum transition frequency ft)impose a limitation on the maximum data rate. To counter thislimitation, multi-level signalling such as PAM-4 or duobinaryhave been used in recent papers [1]–[3] to demonstrate data-rates up to 25Gbps across electrical backplanes.However, although more advanced modulation schemes requireless bandwidth, the processing needed on both the transmittingand the receiving chip significantly increases. Among others,a threshold adjustment circuit (TAC) operating at high speedis needed at the receiving end to seperate different symbollevels. This paper presents a 80GHz TAC designed in a 0.13µmSiGe BiCMOS technology using a current DAC for thresholdadjustment. The large bandwidth and the fine threshold controlof the presented circuit allows duobinary transmission up to80Gbps when signalling over a 40GHz channel.The structure of this paper is the following: in Section IIthe topology of a standard non-clocked duobinary receiveris discussed, Section III presents the circuit that is used toachieve a high speed threshold adjustment, the DACs usedin the control of the threshold level are shown in Section IV,978-1-4799-4994-6/14/$31.00 c©2014 IEEESection V discusses the fabrication of the chip and further workthat has to be done and Section VI summarizes the results andconcludes this paper.II. NON-CLOCKED DUOBINARY RECEIVEROne of the more promising modulation schemes to reducethe required channel bandwidth without adding too muchchip complexity is the duobinary scheme discussed in [4]. Areceiver structure as well as the typical 3-level eyediagramof this modulation scheme is shown in Fig.1. Due to thehigh speeds, a fully differential channel is needed, although,for simplicity, only the single-ended signaling is drawn. Thewideband input amplifier needs a bandwidth comparable tothe channel bandwidth, for a 80Gbps duobinary transmissionthis corresponds to approximately 40GHz. An input bufferachieving this performance is shown in [5]. After the inputbuffer, the signal is split and compared with both a lowerand an upper threshold voltages. To do this comparison, thedifferential signal is first shifted using a TAC. This willposition the zero level of the signal in the middle of thelower and upper eye respectively. This signal is then appliedto a limitting amplifier stage which regenerates a signal withdigital levels, i.e. logic high and logic low above and belowthe threshold respectively, necessary for the XNOR gate, whichwill demodulate the duobinary signal.WidebandamplifierWidebandsplitterVupVlowVupVlowInput duo-binary signalOutputNRZ-signalLimitingamplifierLimitingamplifierFig. 1. Standard non-clocked duobinary receiver as described in [4].III. EMITTER FOLLOWER THRESHOLD ADJUSTMENTCIRCUITThe TAC, as shown in Fig.2 consists of two distinct parts:an emitter follower with threshold adjustment, and a cascodedoutput driver. Both circuits will be discussed in greater detailin the following sections.A. Emitter follower threshold adjustmentThe input of the TAC uses emitter followers (EF), shownas transistors Q0 and Q1 in Fig.2. The transistors are biasedwith a constant current of 3.2mA, which is optimized formaximal bandwith (max ft biasing). The use of EFs has twomain benefits: Firstly, they provide a low output impedance,and as a result allow for a higher bandwidth when drivingthe capacitive input of the cascoded output stage. Secondly,the voltage relationship between base (fixed at 2.4V DC bythe wideband input amplifier) and emitter (given the constantemitter current) is fixed. This results in an equal DC voltageat the emitters of transistors Q0 and Q1. To introduce a shiftin DC voltage, and hence in threshold, a series resistor (R0and R1) is added between the output of the EFs and the inputof the cascoded output stage. The biasing current of the EF issplit into two parts, one directly connected to the emitter, oneconnected through this series resistor. By changing the ratio ofthese two current sources (varying α between 0mA - 1.3mA),the amount of current flowing through the resistor and hencethe DC level at the input of the next stage can be controlled.By varying the DC voltage of the positive and negative inputin the opposite direction, the threshold can be adjusted.Q0Q1R0 C0 R1 C1Vin,PVin,NVout,NVout,PVtac,NVtac,PCascode output driver2.5V 2.5V1.6mA - 1.6mA +1.6mA + 1.6mA -2.5V 2.5V 2.5VFig. 2. Threshold adjustment circuit consisting of emitter followers biasedwith a constant current and the cascade output driver. The threshold level isadjusted by means of α ranging from 0mA - 1.3mA.Furthermore, capacitors C0, C1 are added in parallel withresistors R0,R1 in Fig.2. This provides a low impedance path athigher frequencies between the output of the emitter followersand the input of the cascode, and hence, increase the bandwith.The capacitors used in this circuit are metal-insulator-metal(MIM) capacitors with their bottom plate connected to theemitter of the EFs and their top plate connected to theinput of the cascode output driver. This reduces the parasiticcapacitance at the input of the cascoded amplifier and increasesthe bandwidth. The use of this topology leads to shifting ofsignals with a bandwidth of more than 80GHz as shown inthe post layout simulation results of Fig.3. The variation onthe bandwidth is less than 5% across the whole shifting range.The shifting resistors R0 and R1 have a value of 80Ω in thisdesign. The following trade-off exists: larger values give alarger maximum threshold adjustment but a smaller resolutionand the need for a higher bypass capacitance while smallervalues mainly deteriorate the maximum threshold varation.Parallel with these 80Ω resistors a 1pF MIM capacitor wasimplemented.−6 −4 −2 0 2 4 6−60−40−200204060Time, (ps)Voltage, (mV)80Gbps input duobinary signal−6 −4 −2 0 2 4 6−100−50050Time, (ps)Voltage, (mV)shifted 80Gbps duobinary signalFig. 3. Input eye-diagram of a 80Gbps duobinary input signal together withthe eye-diagram of the shifted version at the output of the threshold adjustmentcircuit.The current mirrors providing the current to the EFs areimplemented as cascoded current mirrors to reduce the effectof the varying collector voltages of the mirror transistor. Thisallows us to have a current resolution of less than 5µA resultingin a voltage shifting resolution of less than 1mV.B. Cascoded output driverThe switching output driver of which the threshold isadjusted, consists of a degenerated differential cascode asshown in Fig.2. By using a cascode, the miller capacitanceat the input can be diminished [6] and the maximally allowedvoltage swing at the output is higher since the peak voltage atthe collector of a common base stage can go up to BVCBO [7],[8]. Feedback by means of resistive degeneration is appliedto increase the bandwidth of the circuit by trading in gain.Furthermore, it makes the cascode less sensitive to differencesin DC-voltage at the input which limits the accuracy that isneeded for the TAC. The biasing of the cascode is such thatthe transistors achieve their maximum ft. The load resistor isa 80Ω poly resistor chosen to allow enough bandwidth whenloaded with the input capacitance of the next stage. The tailcurrent is 5mA.In Fig.3 the output eye-diagram shows a zero-volt level thatcorresponds to the eye-crossing of the upper duobinary eye.By adding a limiting amplifier to this output the wanted NRZ-signal for the upper half of the duobinary signal is obtained.C. Bandwidth and linearityIn Fig.4 the gain and the input referred 1dB compressionpoint are simulated in function of the frequency. The -3dBbandwidth of the circuit is above 80GHz, to ensure that thelevel shifting stage will not limit the bandwidth in a 80Gbpsdata system. The simulated input referred 1dB compressionpoint is around -4dBm.100 101 102−10−8−6−4−2024Frequency, (GHz) Voltage gain, (dB)Input 1dB compression point, (dBm)Fig. 4. Post layout simulation results for the voltage gain and input referred1dB compression point of the TAC in function of the frequency.The 1dB compression point was simulated by driving thepower in a 50Ω input buffer connected in front of the TACand measuring the input power of the TAC and the outputpower of the TAC. Since the linearity of the input buffer isgreater than the linarity of the TAC this is a valid measurefor the linearity. At higher frequencies it is no longer possibleto include a sufficient number of harmonics in the simulation,which leads to a lower simulated 1dB compression point, ascan be noticed from the two rightmost 1dB compression pointsin Fig.4. Verification of the linearity at high frequencies wassubsequentially done by checking the in- and output diagramat different input power levels.IV. DIGITALLY CONTROLLED CURRENT DACSThe circuit used to generate the currents for the EFs isshown in Fig.5, both currents are derived from one variablecurrent source Ivar. This source is implemented as a traditionalbinary weighted current mirror with switchable gates to controlthe total current. The variable current is mirrored and amplifiedfive times. This amplification allows to reduce the current inthe DAC as well as the area consumed by the DAC. However,care has to be taken to meet the matching requirements for the7 bit DAC resolution used in this design.In a second stage the amplified variable current is addedand substracted from a constant current source I0. Using thistechnique the current through the EFs will always be two timesI0. The last stage of the current generator is the implementationof a switch which allows to change the shifting direction.Measurements on the fabricated die showed that the currentIvarI0 I0VddVdd Vdd Vdd VddOutput currentswitchingVswitch(1)(2)Iout1Iout2Fig. 5. Circuit used to generate complementary output currents Iout1 andIout2 from the DAC current Ivar . Sooch cascode current mirrors, subcircuits(1) and (2), are used to get accurate copies of the DAC current. The digitalsignal Vswitch interchanges the output currents.switching circuit has a minimum of 263µA and a maximum of1.26mA, variable in steps of 4µA. Taking into account the 80Ωresistor that converts this current into the level shifting voltageand the times two multiplication in the EF current mirrors, wecan shift the level 160mV up or down in steps of 0.64mV. Thecurrent running through the EFs is constant around 3mA.V. FABRICATION AND FURTHER WORKA chip implementing the discussed threshold adjustmentcircuit has been fabricated in a 0.13µm SiGe BiCMOS technol-ogy with an ft beyond 200GHz. The part of the chip with thediscussed circuit is shown in the micrograph of Fig.6. Althoughthe proposed circuit can not be tested on its own, preliminarymeasurements show that an eye at the input can be shifted overthe complete input range.Fig. 6. Die micrograph of the TAC circuit.Further testing of the chip implementing the discussedcircuit, will include the reception and demodulation of a80Gbps signal over a 40GHz channel. With improvementof the channel bandwidth even higher data rates should beattainable since the bandwidth of the TAC is as high as 80GHz.This means that with a sufficient bandwidth for the input bufferand the channel, a data rate up to 160Gbps becomes possible.VI. CONCLUSION AND RESULTSIn this paper a broadband threshold adjustment circuit capa-ble of level shifting a duobinary data stream with a bandwidthup to 80GHz is presented. The threshold adjustment circuit canshift a differential input signal up or down by 160mV with aresolution of 0.64mV. It operates from a single 2.5V powersupply, consumes only 35mW in a 130µm SiGe BiCMOStechnology and still has an input referred 1dB compressionpoint of approximately -4dBm. Using this circuit it is possibleto demodulate a multitude of modulation schemes (e.g. duobi-nary, PAM-4) at high bandwidths allowing to achieve higherdata rates over channels with limited bandwidth while keepingthe added circuit complexity low.ACKNOWLEDGMENTSThe authors would like to thank the Agency for Innovationby Science and Technology in Flanders (IWT) for supportingthis work.REFERENCES[1] D. Correia, V. Shah, C. Chua, and P. Amleshi, “Performance comparisonof different encoding schemes in backplane channel at 25gbps+,” in Elec-tromagnetic Compatibility (EMC), 2013 IEEE International Symposiumon. IEEE, 2013, pp. 306–311.[2] J. Lee, M.-S. Chen, and H.-D. Wang, “Design and comparison of three20-gb/s backplane transceivers for duobinary, pam4, and nrz data,” Solid-State Circuits, IEEE Journal of, vol. 43, no. 9, pp. 2120–2133, 2008.[3] A. Adamiecki, M. Duelk, and J. Sinsky, “25 gbit/s electrical duobinarytransmission over fr-4 backplanes,” Electronics Letters, vol. 41, no. 14,pp. 826–827, 2005.[4] J. H. Sinsky, M. Duelk, and A. Adamiecki, “High-speed electricalbackplane transmission using duobinary signaling,” Microwave Theoryand Techniques, IEEE Transactions on, vol. 53, no. 1, pp. 152–160,2005.[5] T. De Keulenaer, Y. Ban, Z. Li, and J. Bauwelinck, “Design of a 80gbit/s sige bicmos fully differential input buffer for serial electricalcommunication,” in International Conference on Electronics, Circuitsand Systems (ICECS-2012), 2012, pp. 237–239.[6] E. Sa¨ckinger, Broadband Circuits for Optical Fiber Communications.New York, NY: John Wiley & Sons, 2005.[7] H. Li, H.-M. Rein, T. Suttorp, and J. Bo¨ck, “Fully integrated SiGe VCOswith powerful output buffer for 77-GHz automotive radar systems andapplications around 100 GHz,” IEEE J. Solid-State Circuits, vol. 39, pp.1650–1658, Oct. 2004.[8] M. Rickelt and H.-M. Rein, “Influence of impact-ionization inducedinstabilities on the maximum usable output voltage of Si bipolar transis-tors,” IEEE Trans. Electron Devices, vol. 48, pp. 774–783, Apr. 2001.

A digitally controlled threshold adjustment circuit in a 0.13um SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

https://biblio.ugent.be/publication/5745205/file/5745282.pdf

A digitally controlled threshold adjustment circuit in a 0.13um SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

Abstract

Similar works

Full text

Available Versions

Crossref

Ghent University Academic Bibliography