Desmet, Veerle

Sazeides, Yiannakis

Vrioni, Costas

English

Ghent University Academic Bibliography

Initial Results on the Importance of Protecting Prediction ArraysAgainst Hard-FaultsVeerle Desmet∗ Yiannakis Sazeides+ Costas Vrioni+∗Dept. of Electronics and Information Systems +Dept. of Computer ScienceGhent University, Belgium University of Cyprus, Nicosiaveerle.desmet@elis.UGent.be {yanos,cs03vk1}@cs.ucy.ac.cyAbstractContinuous circuit and wire miniaturization in-creasingly exert more pressure on the computer de-signers to address the issue of reliable operation inthe presence of hard-faults. Virtually all previouswork on hard-fault reliability addresses problemsthat arise when a fault occurs in architectural re-sources, such as the register file or caches. How-ever, hard-faults can happen in non-architecturalresources, such as prediction arrays and replace-ment bits. Although these non-architectural hard-faults do not affect correctness they may degrade aprocessor performance significantly and, therefore,render them as important to deal with as architec-tural hard-faults.In the past, because faults were more rare, it wasacceptable for low-end systems to offer little or noprotection against faults. As a result, mainly pro-cessors used in high availability systems employedadvanced fault-tolerance techniques, such as usingredundant and spare units [1]. With technologyprojections pointing to a dramatic fault increase inprocessors [2] a more general use of fault-tolerancetechniques is emerging.In this research we determine, using previouslyproposed analytical models, under what temper-ature conditions hard-faults in non-architecturalstructures are likely to occur in the same orderof magnitude as hard-faults in architectural units.Furthermore, we quantify the performance impli-cations of hard-faults in two prediction arrays: aline predictor and a return-address-stack. In par-ticular, a simulation based analysis of a high-endprocessor that experiences a single stuck-at fault inone of its most frequently used cells in the return-address-stack and the line predictor, revealed adegradation up to 9% and 3%, respectively. Whena single stuck-at hard-fault occurs in one of theoutput bits the slowdown can be as high as 34% inthe return-address-stack and 19% in the line pre-dictor.The above findings underline the importance toprotect prediction arrays against non-architecturalhard-faults. Our future work will explore the use oflow-overhead detection and correction techniquesfor non-architectural hard-faults that are found tobe more performance critical, to ensure future pro-cessors can operate with minimal degradation atthe presence of non-architectural hard-faults. Wewill leverage existing techniques that have beenproposed for error detection/correction of architec-tural structures, but, non-architectural resourcesmay provide a distinct opportunity for simpler de-tection and correction techniques since they do notrequire a full repair.References[1] P. J. Meaney, S. B. Swaney, P. N. Sanda, andL. Spainhower. IBM z990 soft error detection andrecovery. IEEE Transactions on Device and Mate-rials Reliability, 5(3):419–427, Sept. 2005.[2] J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers.The impact of technology scaling on lifetime relia-bility. In Proceedings of the 34th Annual Interna-tional Conference on Dependable Systems and Net-works, pages 177–186, June 2004.1

Initial results on the importance of protecting prediction arrays against hard-faults

https://biblio.ugent.be/publication/416992/file/448162

Initial results on the importance of protecting prediction arrays against hard-faults

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Ghent University Academic Bibliography